1 /*
2  * Copyright (c) 2016 Intel Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief Designware USB device controller driver private definitions
10  *
11  * This file contains the Designware USB device controller driver private
12  * definitions.
13  */
14 
15 #ifndef ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_
16 #define ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_
17 
18 #include <sys/util.h>
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 /* Number of USB controllers */
25 enum USB_DW_N { USB_DW_0 = 0, USB_DW_NUM };
26 
27 /* USB IN EP index */
28 enum usb_dw_in_ep_idx {
29 	USB_DW_IN_EP_0 = 0,
30 	USB_DW_IN_EP_1,
31 	USB_DW_IN_EP_2,
32 	USB_DW_IN_EP_3,
33 	USB_DW_IN_EP_4,
34 	USB_DW_IN_EP_5,
35 	USB_DW_IN_EP_NUM
36 };
37 
38 /* USB OUT EP index */
39 enum usb_dw_out_ep_idx {
40 	USB_DW_OUT_EP_0 = 0,
41 	USB_DW_OUT_EP_1,
42 	USB_DW_OUT_EP_2,
43 	USB_DW_OUT_EP_3,
44 	USB_DW_OUT_EP_NUM
45 };
46 
47 /* USB IN EP Register block type */
48 struct usb_dw_in_ep_reg {
49 	volatile uint32_t diepctl;
50 	uint32_t reserved;
51 	volatile uint32_t diepint;
52 	uint32_t reserved1;
53 	volatile uint32_t dieptsiz;
54 	volatile uint32_t diepdma;
55 	volatile uint32_t dtxfsts;
56 	uint32_t reserved2;
57 };
58 
59 /* USB OUT EP Register block type */
60 struct usb_dw_out_ep_reg {
61 	volatile uint32_t doepctl;
62 	uint32_t reserved;
63 	volatile uint32_t doepint;
64 	uint32_t reserved1;
65 	volatile uint32_t doeptsiz;
66 	volatile uint32_t doepdma;
67 	uint32_t reserved2;
68 	uint32_t reserved3;
69 };
70 
71 /* USB Register block type */
72 struct usb_dw_reg {
73 	volatile uint32_t gotgctl;
74 	volatile uint32_t gotgint;
75 	volatile uint32_t gahbcfg;
76 	volatile uint32_t gusbcfg;
77 	volatile uint32_t grstctl;
78 	volatile uint32_t gintsts;
79 	volatile uint32_t gintmsk;
80 	volatile uint32_t grxstsr;
81 	volatile uint32_t grxstsp;
82 	volatile uint32_t grxfsiz;
83 	volatile uint32_t gnptxfsiz;
84 	uint32_t reserved[5];
85 	volatile uint32_t gsnpsid;
86 	volatile uint32_t ghwcfg1;
87 	volatile uint32_t ghwcfg2;
88 	volatile uint32_t ghwcfg3;
89 	volatile uint32_t ghwcfg4;
90 	volatile uint32_t gdfifocfg;
91 	uint32_t reserved1[43];
92 	volatile uint32_t dieptxf1;
93 	volatile uint32_t dieptxf2;
94 	volatile uint32_t dieptxf3;
95 	volatile uint32_t dieptxf4;
96 	volatile uint32_t dieptxf5;
97 	uint32_t reserved2[442];
98 	volatile uint32_t dcfg;
99 	volatile uint32_t dctl;
100 	volatile uint32_t dsts;
101 	uint32_t reserved3;
102 	volatile uint32_t diepmsk;
103 	volatile uint32_t doepmsk;
104 	volatile uint32_t daint;
105 	volatile uint32_t daintmsk;
106 	uint32_t reserved4[2];
107 	volatile uint32_t dvbusdis;
108 	volatile uint32_t dvbuspulse;
109 	volatile uint32_t dthrctl;
110 	volatile uint32_t diepempmsk;
111 	uint32_t reserved5[50];
112 	struct usb_dw_in_ep_reg in_ep_reg[USB_DW_IN_EP_NUM];
113 	uint32_t reserved6[80];
114 	struct usb_dw_out_ep_reg out_ep_reg[USB_DW_OUT_EP_NUM];
115 };
116 
117 /* USB register offsets and masks */
118 #define USB_DW_HWCFG4_DEDFIFOMODE BIT(25)
119 #define USB_DW_GUSBCFG_PHY_IF_MASK BIT(3)
120 #define USB_DW_GUSBCFG_PHY_IF_8_BIT (0)
121 #define USB_DW_GUSBCFG_PHY_IF_16_BIT (1<<3)
122 #define USB_DW_GRSTCTL_AHB_IDLE BIT(31)
123 #define USB_DW_GRSTCTL_TX_FNUM_OFFSET (6)
124 #define USB_DW_GRSTCTL_TX_FFLSH BIT(5)
125 #define USB_DW_GRSTCTL_C_SFT_RST BIT(0)
126 #define USB_DW_GAHBCFG_DMA_EN BIT(5)
127 #define USB_DW_GAHBCFG_GLB_INTR_MASK BIT(0)
128 #define USB_DW_DCTL_SFT_DISCON BIT(1)
129 #define USB_DW_GINTSTS_WK_UP_INT BIT(31)
130 #define USB_DW_GINTSTS_OEP_INT BIT(19)
131 #define USB_DW_GINTSTS_IEP_INT BIT(18)
132 #define USB_DW_GINTSTS_ENUM_DONE BIT(13)
133 #define USB_DW_GINTSTS_USB_RST BIT(12)
134 #define USB_DW_GINTSTS_USB_SUSP BIT(11)
135 #define USB_DW_GINTSTS_RX_FLVL BIT(4)
136 #define USB_DW_GINTSTS_OTG_INT BIT(2)
137 #define USB_DW_DCFG_DEV_SPD_USB2_HS (0)
138 #define USB_DW_DCFG_DEV_SPD_USB2_FS (0x1)
139 #define USB_DW_DCFG_DEV_SPD_LS (0x2)
140 #define USB_DW_DCFG_DEV_SPD_FS (0x3)
141 #define USB_DW_DCFG_DEV_ADDR_MASK (0x7F << 4)
142 #define USB_DW_DCFG_DEV_ADDR_OFFSET (4)
143 #define USB_DW_DAINT_IN_EP_INT(ep) (1 << (ep))
144 #define USB_DW_DAINT_OUT_EP_INT(ep) (0x10000 << (ep))
145 #define USB_DW_DEPCTL_EP_ENA BIT(31)
146 #define USB_DW_DEPCTL_EP_DIS BIT(30)
147 #define USB_DW_DEPCTL_SETDOPID BIT(28)
148 #define USB_DW_DEPCTL_SNAK BIT(27)
149 #define USB_DW_DEPCTL_CNAK BIT(26)
150 #define USB_DW_DEPCTL_STALL BIT(21)
151 #define USB_DW_DEPCTL_TXFNUM_OFFSET (22)
152 #define USB_DW_DEPCTL_TXFNUM_MASK (0xf << 22)
153 #define USB_DW_DEPCTL_EP_TYPE_MASK (0x3 << 18)
154 #define USB_DW_DEPCTL_EP_TYPE_OFFSET (18)
155 #define USB_DW_DEPCTL_EP_TYPE_CONTROL (0)
156 #define USB_DW_DEPCTL_EP_TYPE_ISO (0x1)
157 #define USB_DW_DEPCTL_EP_TYPE_BULK (0x2)
158 #define USB_DW_DEPCTL_EP_TYPE_INTERRUPT (0x3)
159 #define USB_DW_DEPCTL_USB_ACT_EP BIT(15)
160 #define USB_DW_DEPCTL0_MSP_MASK (0x3)
161 #define USB_DW_DEPCTL0_MSP_8 (0x3)
162 #define USB_DW_DEPCTL0_MSP_16 (0x2)
163 #define USB_DW_DEPCTL0_MSP_32 (0x1)
164 #define USB_DW_DEPCTL0_MSP_64 (0)
165 #define USB_DW_DEPCTLn_MSP_MASK (0x3FF)
166 #define USB_DW_DEPCTL_MSP_OFFSET (0)
167 #define USB_DW_DOEPTSIZ_SUP_CNT_MASK (0x3 << 29)
168 #define USB_DW_DOEPTSIZ_SUP_CNT_OFFSET (29)
169 #define USB_DW_DOEPTSIZ0_PKT_CNT_MASK (0x1 << 19)
170 #define USB_DW_DOEPTSIZn_PKT_CNT_MASK (0x3FF << 19)
171 #define USB_DW_DIEPTSIZ0_PKT_CNT_MASK (0x3 << 19)
172 #define USB_DW_DIEPTSIZn_PKT_CNT_MASK (0x3FF << 19)
173 #define USB_DW_DEPTSIZ_PKT_CNT_OFFSET (19)
174 #define USB_DW_DEPTSIZ0_XFER_SIZE_MASK (0x7F)
175 #define USB_DW_DEPTSIZn_XFER_SIZE_MASK (0x7FFFF)
176 #define USB_DW_DEPTSIZ_XFER_SIZE_OFFSET (0)
177 #define USB_DW_DIEPINT_XFER_COMPL BIT(0)
178 #define USB_DW_DIEPINT_TX_FEMP BIT(7)
179 #define USB_DW_DIEPINT_XFER_COMPL BIT(0)
180 #define USB_DW_DOEPINT_SET_UP BIT(3)
181 #define USB_DW_DOEPINT_XFER_COMPL BIT(0)
182 #define USB_DW_DSTS_ENUM_SPD_MASK (0x3)
183 #define USB_DW_DSTS_ENUM_SPD_OFFSET (1)
184 #define USB_DW_DSTS_ENUM_LS (2)
185 #define USB_DW_DSTS_ENUM_FS (3)
186 #define USB_DW_GRXSTSR_EP_NUM_MASK (0xF << 0)
187 #define USB_DW_GRXSTSR_PKT_STS_MASK (0xF << 17)
188 #define USB_DW_GRXSTSR_PKT_STS_OFFSET (17)
189 #define USB_DW_GRXSTSR_PKT_CNT_MASK (0x7FF << 4)
190 #define USB_DW_GRXSTSR_PKT_CNT_OFFSET (4)
191 #define USB_DW_GRXSTSR_PKT_STS_OUT_DATA (2)
192 #define USB_DW_GRXSTSR_PKT_STS_OUT_DATA_DONE (3)
193 #define USB_DW_GRXSTSR_PKT_STS_SETUP_DONE (4)
194 #define USB_DW_GRXSTSR_PKT_STS_SETUP (6)
195 #define USB_DW_DTXFSTS_TXF_SPC_AVAIL_MASK (0xFFFF)
196 
197 #define USB_DW_CORE_RST_TIMEOUT_US 10000
198 #define USB_DW_PLL_TIMEOUT_US 100
199 
200 #define USB_DW_EP_FIFO(ep)						\
201 	(*(uint32_t *)(DT_INST_REG_ADDR(0) + 0x1000 * (ep + 1)))
202 /* USB register block base address */
203 #define USB_DW ((struct usb_dw_reg *)DT_INST_REG_ADDR(0))
204 
205 #define DW_USB_IN_EP_NUM		(6)
206 #define DW_USB_OUT_EP_NUM		(4)
207 #define DW_USB_MAX_PACKET_SIZE		(64)
208 
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif /* ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_ */
214