Searched refs:TIMER_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance
18 #define TIMER_BASE_ADDR DT_INST_REG_ADDR(0) macro67 reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()69 sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()83 return sys_read32(TIMER_BASE_ADDR + CMCNT1_OFFSET); in sys_clock_cycle_get_32()109 sys_write32(CLKEN0 | CLKEN1, TIMER_BASE_ADDR + CMCLKE); in sys_clock_driver_init()112 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()114 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()116 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()118 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()122 TIMER_BASE_ADDR + CMCSR0_OFFSET); in sys_clock_driver_init()[all …]
21 #define TIMER_BASE_ADDR DT_INST_REG_ADDR(0) macro59 return sys_read32(TIMER_BASE_ADDR + XTTCPS_COUNT_VALUE_OFFSET); in read_count()72 sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in update_match()83 sys_read32(TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET); in ttc_isr()155 TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()164 TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()165 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET); in sys_clock_driver_init()166 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET); in sys_clock_driver_init()167 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()168 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET); in sys_clock_driver_init()[all …]
