1 /* 2 * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 /** 7 * @file SoC configuration macros for the Atmel SAM4L family processors. 8 */ 9 10 #ifndef _ATMEL_SAM4L_SOC_H_ 11 #define _ATMEL_SAM4L_SOC_H_ 12 13 #ifndef _ASMLANGUAGE 14 15 #define DONT_USE_CMSIS_INIT 16 #define DONT_USE_PREDEFINED_CORE_HANDLERS 17 #define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS 18 19 #if defined(CONFIG_SOC_PART_NUMBER_SAM4LS8C) 20 #include <sam4ls8c.h> 21 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8B) 22 #include <sam4ls8b.h> 23 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8A) 24 #include <sam4ls8a.h> 25 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4C) 26 #include <sam4ls4c.h> 27 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4B) 28 #include <sam4ls4b.h> 29 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4A) 30 #include <sam4ls4a.h> 31 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2C) 32 #include <sam4ls2c.h> 33 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2B) 34 #include <sam4ls2b.h> 35 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2A) 36 #include <sam4ls2a.h> 37 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8C) 38 #include <sam4lc8c.h> 39 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8B) 40 #include <sam4lc8b.h> 41 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8A) 42 #include <sam4lc8a.h> 43 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4C) 44 #include <sam4lc4c.h> 45 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4B) 46 #include <sam4lc4b.h> 47 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4A) 48 #include <sam4lc4a.h> 49 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2C) 50 #include <sam4lc2c.h> 51 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2B) 52 #include <sam4lc2b.h> 53 #elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2A) 54 #include <sam4lc2a.h> 55 #else 56 #error Library does not support the specified device. 57 #endif 58 59 #include "../common/soc_pmc.h" 60 #include "../common/soc_gpio.h" 61 #include "../common/atmel_sam_dt.h" 62 63 /** Processor Clock (HCLK) Frequency */ 64 #define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ 65 66 /** Master Clock (MCK) Frequency */ 67 #define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ 68 69 /** Oscillator identifiers 70 * External Oscillator 0 71 * External 32 kHz oscillator 72 * Internal 32 kHz RC oscillator 73 * Internal 80 MHz RC oscillator 74 * Internal 4-8-12 MHz RCFAST oscillator 75 * Internal 1 MHz RC oscillator 76 * Internal System RC oscillator 77 */ 78 #define OSC_ID_OSC0 0 79 #define OSC_ID_OSC32 1 80 #define OSC_ID_RC32K 2 81 #define OSC_ID_RC80M 3 82 #define OSC_ID_RCFAST 4 83 #define OSC_ID_RC1M 5 84 #define OSC_ID_RCSYS 6 85 86 /** System clock source 87 * System RC oscillator 88 * Oscillator 0 89 * Phase Locked Loop 0 90 * Digital Frequency Locked Loop 91 * 80 MHz RC oscillator 92 * 4-8-12 MHz RC oscillator 93 * 1 MHz RC oscillator 94 */ 95 #define OSC_SRC_RCSYS 0 96 #define OSC_SRC_OSC0 1 97 #define OSC_SRC_PLL0 2 98 #define OSC_SRC_DFLL 3 99 #define OSC_SRC_RC80M 4 100 #define OSC_SRC_RCFAST 5 101 #define OSC_SRC_RC1M 6 102 103 #define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) 104 105 /** Bus index of maskable module clocks. Peripheral ids are defined out of 106 * order. It start from PBA up to PBD, then move to HSB, and finaly CPU. 107 */ 108 #define PM_CLK_GRP_CPU 5 109 #define PM_CLK_GRP_HSB 4 110 #define PM_CLK_GRP_PBA 0 111 #define PM_CLK_GRP_PBB 1 112 #define PM_CLK_GRP_PBC 2 113 #define PM_CLK_GRP_PBD 3 114 115 /** Clocks derived from the CPU clock 116 */ 117 #define SYSCLK_OCD 0 118 119 /** Clocks derived from the HSB clock 120 */ 121 #define SYSCLK_PDCA_HSB 0 122 #define SYSCLK_HFLASHC_DATA 1 123 #define SYSCLK_HRAMC1_DATA 2 124 #define SYSCLK_USBC_DATA 3 125 #define SYSCLK_CRCCU_DATA 4 126 #define SYSCLK_PBA_BRIDGE 5 127 #define SYSCLK_PBB_BRIDGE 6 128 #define SYSCLK_PBC_BRIDGE 7 129 #define SYSCLK_PBD_BRIDGE 8 130 #define SYSCLK_AESA_HSB 9 131 132 /** Clocks derived from the PBA clock 133 */ 134 #define SYSCLK_IISC 0 135 #define SYSCLK_SPI 1 136 #define SYSCLK_TC0 2 137 #define SYSCLK_TC1 3 138 #define SYSCLK_TWIM0 4 139 #define SYSCLK_TWIS0 5 140 #define SYSCLK_TWIM1 6 141 #define SYSCLK_TWIS1 7 142 #define SYSCLK_USART0 8 143 #define SYSCLK_USART1 9 144 #define SYSCLK_USART2 10 145 #define SYSCLK_USART3 11 146 #define SYSCLK_ADCIFE 12 147 #define SYSCLK_DACC 13 148 #define SYSCLK_ACIFC 14 149 #define SYSCLK_GLOC 15 150 #define SYSCLK_ABDACB 16 151 #define SYSCLK_TRNG 17 152 #define SYSCLK_PARC 18 153 #define SYSCLK_CATB 19 154 #define SYSCLK_TWIM2 21 155 #define SYSCLK_TWIM3 22 156 #define SYSCLK_LCDCA 23 157 158 /** Clocks derived from the PBB clock 159 */ 160 #define SYSCLK_HFLASHC_REGS 0 161 #define SYSCLK_HRAMC1_REGS 1 162 #define SYSCLK_HMATRIX 2 163 #define SYSCLK_PDCA_PB 3 164 #define SYSCLK_CRCCU_REGS 4 165 #define SYSCLK_USBC_REGS 5 166 #define SYSCLK_PEVC 6 167 168 /** Clocks derived from the PBC clock 169 */ 170 #define SYSCLK_PM 0 171 #define SYSCLK_CHIPID 1 172 #define SYSCLK_SCIF 2 173 #define SYSCLK_FREQM 3 174 #define SYSCLK_GPIO 4 175 176 /** Clocks derived from the PBD clock 177 */ 178 #define SYSCLK_BPM 0 179 #define SYSCLK_BSCIF 1 180 #define SYSCLK_AST 2 181 #define SYSCLK_WDT 3 182 #define SYSCLK_EIC 4 183 #define SYSCLK_PICOUART 5 184 185 /** Divided clock mask derived from the PBA clock 186 */ 187 #define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) 188 #define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) 189 #define PBA_DIVMASK_CLK_USART (1u << 2) 190 #define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) 191 #define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) 192 #define PBA_DIVMASK_Msk (0x7Fu << 0) 193 194 /** Generic Clock Instances 195 * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) 196 * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) 197 * 2- AST and GCLK2 pin 198 * 3- CATB and GCLK3 pin 199 * 4- AESA 200 * 5- GLOC, TC0 and RC32KIFB_REF 201 * 6- ABDACB and IISC 202 * 7- USBC 203 * 8- TC1 and PEVC[0] 204 * 9- PLL0 and PEVC[1] 205 * 10- ADCIFE 206 * 11- Master generic clock. Can be used as source for other generic clocks. 207 */ 208 #define GEN_CLK_DFLL_REF 0 209 #define GEN_CLK_DFLL_DITHER 1 210 #define GEN_CLK_AST 2 211 #define GEN_CLK_CATB 3 212 #define GEN_CLK_AESA 4 213 #define GEN_CLK_GLOC 5 214 #define GEN_CLK_ABDACB 6 215 #define GEN_CLK_USBC 7 216 #define GEN_CLK_TC1_PEVC0 8 217 #define GEN_CLK_PLL0_PEVC1 9 218 #define GEN_CLK_ADCIFE 10 219 #define GEN_CLK_MASTER_GEN 11 220 221 #endif /* !_ASMLANGUAGE */ 222 223 #endif /* _ATMEL_SAM4L_SOC_H_ */ 224
