STM32_PLL_P_DIVISOR (reference) in projects: Zephyr-Core-2.7.6

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Searched refs:STM32_PLL_P_DIVISOR (Results 1 – 3 of 3) sorted by relevance

/Zephyr-Core-2.7.6/drivers/clock_control/
D	clock_stm32f2_f4_f7.c	`35 pllinit->PLLP = pllp(STM32_PLL_P_DIVISOR); in config_pll_init()`
D	clock_stm32_ll_h7.c	`78 STM32_PLL_P_DIVISOR) 636 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); in stm32_clock_control_init()`
/Zephyr-Core-2.7.6/include/drivers/clock_control/
D	stm32_clock_control.h	`176 #define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p) macro 182 #define STM32_PLL_P_DIVISOR CONFIG_CLOCK_STM32_PLL_P_DIVISOR macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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babblesim_ext_2G4_device_playback-3.7.0
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