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Searched refs:STM32_PLL3_M_DIVISOR (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-2.7.6/include/drivers/clock_control/
Dstm32_clock_control.h189 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) macro
199 #define STM32_PLL3_M_DIVISOR CONFIG_CLOCK_STM32_PLL3_M_DIVISOR macro
/Zephyr-Core-2.7.6/drivers/clock_control/
Dclock_stm32_ll_h7.c725 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range); in stm32_clock_control_init()
734 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR); in stm32_clock_control_init()