1 /*
2  * Copyright (c) 2020 Nuvoton Technology Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9 
10 /*
11  * NPCX register structure size/offset checking macro function to mitigate
12  * the risk of unexpected compiling results. All addresses of NPCX registers
13  * must meet the alignment requirement of cortex-m4.
14  * DO NOT use 'packed' attribute if module contains different length ie.
15  * 8/16/32 bits registers.
16  */
17 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
18 	BUILD_ASSERT(sizeof(struct reg_def) == size, \
19 		"Failed in size check of register structure!")
20 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
21 	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
22 		"Failed in offset check of register structure member!")
23 
24 /*
25  * NPCX register access checking via structure macro function to mitigate the
26  * risk of unexpected compiling results if module contains different length
27  * registers. For example, a word register access might break into two byte
28  * register accesses by adding 'packed' attribute.
29  *
30  * For example, add this macro for word register 'PRSC' of PWM module in its
31  * device init function for checking violation. Once it occurred, core will be
32  * stalled forever and easy to find out what happens.
33  */
34 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
35 		uint16_t placeholder = reg; \
36 		reg = val; \
37 		__ASSERT(reg == val, "16-bit reg access failed!"); \
38 		reg = placeholder; \
39 	}
40 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
41 		uint32_t placeholder = reg; \
42 		reg = val; \
43 		__ASSERT(reg == val, "32-bit reg access failed!"); \
44 		reg = placeholder; \
45 	}
46 /*
47  * Core Domain Clock Generator (CDCG) device registers
48  */
49 struct cdcg_reg {
50 	/* High Frequency Clock Generator (HFCG) registers */
51 	/* 0x000: HFCG Control */
52 	volatile uint8_t HFCGCTRL;
53 	volatile uint8_t reserved1;
54 	/* 0x002: HFCG M Low Byte Value */
55 	volatile uint8_t HFCGML;
56 	volatile uint8_t reserved2;
57 	/* 0x004: HFCG M High Byte Value */
58 	volatile uint8_t HFCGMH;
59 	volatile uint8_t reserved3;
60 	/* 0x006: HFCG N Value */
61 	volatile uint8_t HFCGN;
62 	volatile uint8_t reserved4;
63 	/* 0x008: HFCG Prescaler */
64 	volatile uint8_t HFCGP;
65 	volatile uint8_t reserved5[7];
66 	/* 0x010: HFCG Bus Clock Dividers */
67 	volatile uint8_t HFCBCD;
68 	volatile uint8_t reserved6;
69 	/* 0x012: HFCG Bus Clock Dividers */
70 	volatile uint8_t HFCBCD1;
71 	volatile uint8_t reserved7;
72 	/* 0x014: HFCG Bus Clock Dividers */
73 	volatile uint8_t HFCBCD2;
74 	volatile uint8_t reserved8[235];
75 
76 	/* Low Frequency Clock Generator (LFCG) registers */
77 	/* 0x100: LFCG Control */
78 	volatile uint8_t  LFCGCTL;
79 	volatile uint8_t reserved9;
80 	/* 0x102: High-Frequency Reference Divisor I */
81 	volatile uint16_t HFRDI;
82 	/* 0x104: High-Frequency Reference Divisor F */
83 	volatile uint16_t HFRDF;
84 	/* 0x106: FRCLK Clock Divisor */
85 	volatile uint16_t FRCDIV;
86 	/* 0x108: Divisor Correction Value 1 */
87 	volatile uint16_t DIVCOR1;
88 	/* 0x10A: Divisor Correction Value 2 */
89 	volatile uint16_t DIVCOR2;
90 	volatile uint8_t reserved10[8];
91 	/* 0x114: LFCG Control 2 */
92 	volatile uint8_t  LFCGCTL2;
93 	volatile uint8_t  reserved11;
94 };
95 
96 /* CDCG register fields */
97 #define NPCX_HFCGCTRL_LOAD                    0
98 #define NPCX_HFCGCTRL_LOCK                    2
99 #define NPCX_HFCGCTRL_CLK_CHNG                7
100 
101 #define NPCX_LFCGCTL2_XT_OSC_SL_EN            6
102 
103 /*
104  * Power Management Controller (PMC) device registers
105  */
106 struct pmc_reg {
107 	/* 0x000: Power Management Controller */
108 	volatile uint8_t PMCSR;
109 	volatile uint8_t reserved1[2];
110 	/* 0x003: Enable in Sleep Control */
111 	volatile uint8_t ENIDL_CTL;
112 	/* 0x004: Disable in Idle Control */
113 	volatile uint8_t DISIDL_CTL;
114 	/* 0x005: Disable in Idle Control 1 */
115 	volatile uint8_t DISIDL_CTL1;
116 	volatile uint8_t reserved2[2];
117 	/* 0x008 - 0D: Power-Down Control 1 - 6 */
118 	volatile uint8_t PWDWN_CTL1[6];
119 	volatile uint8_t reserved3[18];
120 	/* 0x020 - 21: Power-Down Control 1 - 2 */
121 	volatile uint8_t RAM_PD[2];
122 	volatile uint8_t reserved4[2];
123 	/* 0x024: Power-Down Control 7 */
124 	volatile uint8_t PWDWN_CTL7[1];
125 };
126 
127 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)128 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
129 {
130 	if (ctl_no < 6) {
131 		return 0x008 + ctl_no;
132 	} else {
133 		return 0x024 + ctl_no - 6;
134 	}
135 }
136 
137 /* Macro functions for PMC multi-registers */
138 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
139 						npcx_pwdwn_ctl_offset(n)))
140 
141 /* PMC register fields */
142 #define NPCX_PMCSR_DI_INSTW                   0
143 #define NPCX_PMCSR_DHF                        1
144 #define NPCX_PMCSR_IDLE                       2
145 #define NPCX_PMCSR_NWBI                       3
146 #define NPCX_PMCSR_OHFC                       6
147 #define NPCX_PMCSR_OLFC                       7
148 #define NPCX_DISIDL_CTL_RAM_DID               5
149 #define NPCX_ENIDL_CTL_ADC_LFSL               7
150 #define NPCX_ENIDL_CTL_LP_WK_CTL              6
151 #define NPCX_ENIDL_CTL_PECI_ENI               2
152 #define NPCX_ENIDL_CTL_ADC_ACC_DIS            1
153 
154 /*
155  * System Configuration (SCFG) device registers
156  */
157 struct scfg_reg {
158 	/* 0x000: Device Control */
159 	volatile uint8_t DEVCNT;
160 	/* 0x001: Straps Status */
161 	volatile uint8_t STRPST;
162 	/* 0x002: Reset Control and Status */
163 	volatile uint8_t RSTCTL;
164 	volatile uint8_t reserved1[3];
165 	/* 0x006: Device Control 4 */
166 	volatile uint8_t DEV_CTL4;
167 	volatile uint8_t reserved2[9];
168 	/* 0x010 - 1F: Device Alternate Function 0 - F */
169 	volatile uint8_t DEVALT0[16];
170 	volatile uint8_t reserved3[6];
171 	/* 0x026: Low-Voltage GPIO Pins Control 5 */
172 	volatile uint8_t LV_GPIO_CTL5[1];
173 	volatile uint8_t reserved4;
174 	/* 0x028: Pull-Up/Pull-Down Enable 0 */
175 	volatile uint8_t PUPD_EN0;
176 	/* 0x029: Pull-Up/Pull-Down Enable 1 */
177 	volatile uint8_t PUPD_EN1;
178 	/* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
179 	volatile uint8_t LV_GPIO_CTL0[5];
180 };
181 
182 /* SCFG internal inline functions for multi-registers */
npcx_devalt_offset(uint32_t alt_no)183 static inline uint32_t npcx_devalt_offset(uint32_t alt_no)
184 {
185 	return 0x010 + alt_no;
186 }
187 
npcx_lv_gpio_ctl_offset(uint32_t ctl_no)188 static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
189 {
190 	if (ctl_no < 5) {
191 		return 0x02a + ctl_no;
192 	} else {
193 		return 0x026 + ctl_no - 5;
194 	}
195 }
196 
197 /* Macro functions for SCFG multi-registers */
198 #define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
199 						npcx_devalt_offset(n)))
200 #define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \
201 						npcx_lv_gpio_ctl_offset(n)))
202 
203 /* SCFG register fields */
204 #define NPCX_DEVCNT_F_SPI_TRIS                6
205 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD         FIELD(2, 2)
206 #define NPCX_DEVCNT_JEN1_HEN                  5
207 #define NPCX_DEVCNT_JEN0_HEN                  4
208 #define NPCX_STRPST_TRIST                     1
209 #define NPCX_STRPST_TEST                      2
210 #define NPCX_STRPST_JEN1                      4
211 #define NPCX_STRPST_JEN0                      5
212 #define NPCX_STRPST_SPI_COMP                  7
213 #define NPCX_RSTCTL_VCC1_RST_STS              0
214 #define NPCX_RSTCTL_DBGRST_STS                1
215 #define NPCX_RSTCTL_VCC1_RST_SCRATCH          3
216 #define NPCX_RSTCTL_LRESET_PLTRST_MODE        5
217 #define NPCX_RSTCTL_HIPRST_MODE               6
218 #define NPCX_DEV_CTL4_F_SPI_SLLK              2
219 #define NPCX_DEV_CTL4_SPI_SP_SEL              4
220 #define NPCX_DEV_CTL4_WP_IF                   5
221 #define NPCX_DEV_CTL4_VCC1_RST_LK             6
222 #define NPCX_DEVPU0_I2C0_0_PUE                0
223 #define NPCX_DEVPU0_I2C0_1_PUE                1
224 #define NPCX_DEVPU0_I2C1_0_PUE                2
225 #define NPCX_DEVPU0_I2C2_0_PUE                4
226 #define NPCX_DEVPU0_I2C3_0_PUE                6
227 #define NPCX_DEVPU1_F_SPI_PUD_EN              7
228 
229 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
230 enum npcx_hif_type {
231 	NPCX_HIF_TYPE_NONE,
232 	NPCX_HIF_TYPE_LPC,
233 	NPCX_HIF_TYPE_ESPI_SHI,
234 };
235 
236 /*
237  * System Glue (GLUE) device registers
238  */
239 struct glue_reg {
240 	volatile uint8_t reserved1[2];
241 	/* 0x002: SMBus Start Bit Detection */
242 	volatile uint8_t SMB_SBD;
243 	/* 0x003: SMBus Event Enable */
244 	volatile uint8_t SMB_EEN;
245 	volatile uint8_t reserved2[12];
246 	/* 0x010: Simple Debug Port Data 0 */
247 	volatile uint8_t SDPD0;
248 	volatile uint8_t reserved3;
249 	/* 0x012: Simple Debug Port Data 1 */
250 	volatile uint8_t SDPD1;
251 	volatile uint8_t reserved4;
252 	/* 0x014: Simple Debug Port Control and Status */
253 	volatile uint8_t SDP_CTS;
254 	volatile uint8_t reserved5[12];
255 	/* 0x021: SMBus Bus Select */
256 	volatile uint8_t SMB_SEL;
257 	volatile uint8_t reserved6[5];
258 	/* 0x027: PSL Control and Status */
259 	volatile uint8_t PSL_CTS;
260 };
261 
262 /*
263  * Universal Asynchronous Receiver-Transmitter (UART) device registers
264  */
265 struct uart_reg {
266 	/* 0x000: Transmit Data Buffer */
267 	volatile uint8_t UTBUF;
268 	volatile uint8_t reserved1;
269 	/* 0x002: Receive Data Buffer */
270 	volatile uint8_t URBUF;
271 	volatile uint8_t reserved2;
272 	/* 0x004: Interrupt Control */
273 	volatile uint8_t UICTRL;
274 	volatile uint8_t reserved3;
275 	/* 0x006: Status */
276 	volatile uint8_t USTAT;
277 	volatile uint8_t reserved4;
278 	/* 0x008: Frame Select */
279 	volatile uint8_t UFRS;
280 	volatile uint8_t reserved5;
281 	/* 0x00A: Mode Select */
282 	volatile uint8_t UMDSL;
283 	volatile uint8_t reserved6;
284 	/* 0x00C: Baud Rate Divisor */
285 	volatile uint8_t UBAUD;
286 	volatile uint8_t reserved7;
287 	/* 0x00E: Baud Rate Prescaler */
288 	volatile uint8_t UPSR;
289 	volatile uint8_t reserved8[17];
290 	/* 0x020: FIFO Mode Transmit Status */
291 	volatile uint8_t UFTSTS;
292 	volatile uint8_t reserved9;
293 	/* 0x022: FIFO Mode Receive Status */
294 	volatile uint8_t UFRSTS;
295 	volatile uint8_t reserved10;
296 	/* 0x024: FIFO Mode Transmit Control */
297 	volatile uint8_t UFTCTL;
298 	volatile uint8_t reserved11;
299 	/* 0x026: FIFO Mode Receive Control */
300 	volatile uint8_t UFRCTL;
301 };
302 
303 /* UART register fields */
304 #define NPCX_UICTRL_TBE                       0
305 #define NPCX_UICTRL_RBF                       1
306 #define NPCX_UICTRL_ETI                       5
307 #define NPCX_UICTRL_ERI                       6
308 #define NPCX_UICTRL_EEI                       7
309 #define NPCX_USTAT_PE                         0
310 #define NPCX_USTAT_FE                         1
311 #define NPCX_USTAT_DOE                        2
312 #define NPCX_USTAT_ERR                        3
313 #define NPCX_USTAT_BKD                        4
314 #define NPCX_USTAT_RB9                        5
315 #define NPCX_USTAT_XMIP                       6
316 #define NPCX_UFRS_CHAR_FIELD                  FIELD(0, 2)
317 #define NPCX_UFRS_STP                         2
318 #define NPCX_UFRS_XB9                         3
319 #define NPCX_UFRS_PSEL_FIELD                  FIELD(4, 2)
320 #define NPCX_UFRS_PEN                         6
321 #define NPCX_UMDSL_FIFO_MD                    0
322 #define NPCX_UFTSTS_TEMPTY_LVL                FIELD(0, 5)
323 #define NPCX_UFTSTS_TEMPTY_LVL_STS            5
324 #define NPCX_UFTSTS_TFIFO_EMPTY_STS           6
325 #define NPCX_UFTSTS_NXMIP                     7
326 #define NPCX_UFRSTS_RFULL_LVL_STS             5
327 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS          6
328 #define NPCX_UFRSTS_ERR                       7
329 #define NPCX_UFTCTL_TEMPTY_LVL_SEL            FIELD(0, 5)
330 #define NPCX_UFTCTL_TEMPTY_LVL_EN             5
331 #define NPCX_UFTCTL_TEMPTY_EN                 6
332 #define NPCX_UFTCTL_NXMIPEN                   7
333 #define NPCX_UFRCTL_RFULL_LVL_SEL             FIELD(0, 5)
334 #define NPCX_UFRCTL_RFULL_LVL_EN              5
335 #define NPCX_UFRCTL_RNEMPTY_EN                6
336 #define NPCX_UFRCTL_ERR_EN                    7
337 
338 /*
339  * Multi-Input Wake-Up Unit (MIWU) device registers
340  */
341 
342 /* MIWU internal inline functions for multi-registers */
npcx_wkedg_offset(uint32_t group)343 static inline uint32_t npcx_wkedg_offset(uint32_t group)
344 {
345 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
346 		return 0x000 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
347 	} else { /* NPCX9 and later series */
348 		return 0x000 + group * 0x10UL;
349 	}
350 }
351 
npcx_wkaedg_offset(uint32_t group)352 static inline uint32_t npcx_wkaedg_offset(uint32_t group)
353 {
354 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
355 		return 0x001 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
356 	} else { /* NPCX9 and later series */
357 		return 0x001 + group * 0x10ul;
358 	}
359 }
360 
npcx_wkmod_offset(uint32_t group)361 static inline uint32_t npcx_wkmod_offset(uint32_t group)
362 {
363 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
364 		return 0x070 + group;
365 	} else { /* NPCX9 and later series */
366 		return 0x002 + group * 0x10ul;
367 	}
368 }
369 
npcx_wkpnd_offset(uint32_t group)370 static inline uint32_t npcx_wkpnd_offset(uint32_t group)
371 {
372 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
373 		return 0x00a + (group * 4ul) + (group < 5 ? 0 : 0x10);
374 	} else { /* NPCX9 and later series */
375 		return 0x003 + group * 0x10ul;
376 	}
377 }
378 
npcx_wkpcl_offset(uint32_t group)379 static inline uint32_t npcx_wkpcl_offset(uint32_t group)
380 {
381 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
382 		return 0x00c + (group * 4ul) + (group < 5 ? 0 : 0x10);
383 	} else { /* NPCX9 and later series */
384 		return 0x004 + group * 0x10ul;
385 	}
386 }
387 
npcx_wken_offset(uint32_t group)388 static inline uint32_t npcx_wken_offset(uint32_t group)
389 {
390 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
391 		return 0x01e + (group * 2ul) + (group < 5 ? 0 : 0x12);
392 	} else { /* NPCX9 and later series */
393 		return 0x005 + group * 0x10ul;
394 	}
395 }
396 
npcx_wkst_offset(uint32_t group)397 static inline uint32_t npcx_wkst_offset(uint32_t group)
398 {
399 	/* NPCX9 and later series only */
400 	return 0x006 + group * 0x10ul;
401 }
402 
npcx_wkinen_offset(uint32_t group)403 static inline uint32_t npcx_wkinen_offset(uint32_t group)
404 {
405 	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
406 		return 0x01f + (group * 2ul) + (group < 5 ? 0 : 0x12);
407 	} else { /* NPCX9 and later series */
408 		return 0x007 + group * 0x10ul;
409 	}
410 }
411 
412 /* Macro functions for MIWU multi-registers */
413 #define NPCX_WKEDG(base, group) \
414 	(*(volatile uint8_t *)(base +  npcx_wkedg_offset(group)))
415 #define NPCX_WKAEDG(base, group) \
416 	(*(volatile uint8_t *)(base + npcx_wkaedg_offset(group)))
417 #define NPCX_WKPND(base, group) \
418 	(*(volatile uint8_t *)(base + npcx_wkpnd_offset(group)))
419 #define NPCX_WKPCL(base, group) \
420 	(*(volatile uint8_t *)(base + npcx_wkpcl_offset(group)))
421 #define NPCX_WKEN(base, group) \
422 	(*(volatile uint8_t *)(base + npcx_wken_offset(group)))
423 #define NPCX_WKINEN(base, group) \
424 	(*(volatile uint8_t *)(base + npcx_wkinen_offset(group)))
425 #define NPCX_WKMOD(base, group) \
426 	(*(volatile uint8_t *)(base + npcx_wkmod_offset(group)))
427 
428 /*
429  * General-Purpose I/O (GPIO) device registers
430  */
431 struct gpio_reg {
432 	/* 0x000: Port GPIOx Data Out */
433 	volatile uint8_t PDOUT;
434 	/* 0x001: Port GPIOx Data In */
435 	volatile uint8_t PDIN;
436 	/* 0x002: Port GPIOx Direction */
437 	volatile uint8_t PDIR;
438 	/* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
439 	volatile uint8_t PPULL;
440 	/* 0x004: Port GPIOx Pull-Up/Down Selection */
441 	volatile uint8_t PPUD;
442 	/* 0x005: Port GPIOx Drive Enable by VDD Present */
443 	volatile uint8_t PENVDD;
444 	/* 0x006: Port GPIOx Output Type */
445 	volatile uint8_t PTYPE;
446 	/* 0x007: Port GPIOx Lock Control */
447 	volatile uint8_t PLOCK_CTL;
448 };
449 
450 /*
451  * Pulse Width Modulator (PWM) device registers
452  */
453 struct pwm_reg {
454 	/* 0x000: Clock Prescaler */
455 	volatile uint16_t PRSC;
456 	/* 0x002: Cycle Time */
457 	volatile uint16_t CTR;
458 	/* 0x004: PWM Control */
459 	volatile uint8_t PWMCTL;
460 	volatile uint8_t reserved1;
461 	/* 0x006: Duty Cycle */
462 	volatile uint16_t DCR;
463 	volatile uint8_t reserved2[4];
464 	/* 0x00C: PWM Control Extended */
465 	volatile uint8_t PWMCTLEX;
466 	volatile uint8_t reserved3;
467 };
468 
469 /* PWM register fields */
470 #define NPCX_PWMCTL_INVP                      0
471 #define NPCX_PWMCTL_CKSEL                     1
472 #define NPCX_PWMCTL_HB_DC_CTL_FIELD           FIELD(2, 2)
473 #define NPCX_PWMCTL_PWR                       7
474 #define NPCX_PWMCTLEX_FCK_SEL_FIELD           FIELD(4, 2)
475 #define NPCX_PWMCTLEX_OD_OUT                  7
476 
477 /*
478  * Analog-To-Digital Converter (ADC) device registers
479  */
480 struct adc_reg {
481 	/* 0x000: ADC Status */
482 	volatile uint16_t ADCSTS;
483 	/* 0x002: ADC Configuration */
484 	volatile uint16_t ADCCNF;
485 	/* 0x004: ADC Timing Control */
486 	volatile uint16_t ATCTL;
487 	/* 0x006: ADC Single Channel Address */
488 	volatile uint16_t ASCADD;
489 	/* 0x008: ADC Scan Channels Select */
490 	volatile uint16_t ADCCS;
491 	volatile uint8_t reserved1[10];
492 	/* 0x014: Threshold Control 1 */
493 	volatile uint16_t THRCTL1;
494 	/* 0x016: Threshold Control 2 */
495 	volatile uint16_t THRCTL2;
496 	/* 0x018: Threshold Control 3 */
497 	volatile uint16_t THRCTL3;
498 	/* 0x01A:  Threshold Status */
499 	volatile uint16_t THRCTS;
500 	volatile uint8_t reserved2[4];
501 	/* 0x020: Internal register 1 for ADC Speed */
502 	volatile uint16_t ADCCNF2;
503 	/* 0x022: Internal register 2 for ADC Speed */
504 	volatile uint16_t GENDLY;
505 	volatile uint8_t reserved3[2];
506 	/* 0x026: Internal register 3 for ADC Speed */
507 	volatile uint16_t MEAST;
508 	volatile uint8_t reserved4[18];
509 	/* 0x03A: Deassertion Threshold Control 1 Word */
510 	volatile uint16_t THR_DCTL1;
511 	/* 0x03C: Deassertion Threshold Control 2 Word */
512 	volatile uint16_t THR_DCTL2;
513 	/* 0x03E: Deassertion Threshold Control 3 Word */
514 	volatile uint16_t THR_DCTL3;
515 	/* 0x040 - 52: Data Buffer of Channel 0 - 9 */
516 	volatile uint16_t CHNDAT[10];
517 };
518 
519 /* ADC register fields */
520 #define NPCX_ATCTL_SCLKDIV_FIELD              FIELD(0, 6)
521 #define NPCX_ATCTL_DLY_FIELD                  FIELD(8, 3)
522 #define NPCX_ASCADD_SADDR_FIELD               FIELD(0, 5)
523 #define NPCX_ADCSTS_EOCEV                     0
524 #define NPCX_ADCSTS_EOCCEV                    1
525 #define NPCX_ADCCNF_ADCMD_FIELD               FIELD(1, 2)
526 #define NPCX_ADCCNF_ADCRPTC                   3
527 #define NPCX_ADCCNF_INTECEN                   6
528 #define NPCX_ADCCNF_START                     4
529 #define NPCX_ADCCNF_ADCEN                     0
530 #define NPCX_ADCCNF_STOP                      11
531 #define NPCX_CHNDAT_CHDAT_FIELD               FIELD(0, 10)
532 #define NPCX_CHNDAT_NEW                       15
533 #define NPCX_THRCTL_THEN                      15
534 #define NPCX_THRCTL_L_H                       14
535 #define NPCX_THRCTL_CHNSEL                    FIELD(10, 4)
536 #define NPCX_THRCTL_THRVAL                    FIELD(0, 10)
537 #define NPCX_THRCTS_ADC_WKEN                  15
538 #define NPCX_THRCTS_THR3_IEN                  10
539 #define NPCX_THRCTS_THR2_IEN                  9
540 #define NPCX_THRCTS_THR1_IEN                  8
541 #define NPCX_THRCTS_ADC_EVENT                 7
542 #define NPCX_THRCTS_THR3_STS                  2
543 #define NPCX_THRCTS_THR2_STS                  1
544 #define NPCX_THRCTS_THR1_STS                  0
545 #define NPCX_THR_DCTL_THRD_EN                 15
546 #define NPCX_THR_DCTL_THR_DVAL                FIELD(0, 10)
547 
548 /*
549  * Timer Watchdog (TWD) device registers
550  */
551 struct twd_reg {
552 	/* 0x000: Timer and Watchdog Configuration */
553 	volatile uint8_t TWCFG;
554 	volatile uint8_t reserved1;
555 	/* 0x002: Timer and Watchdog Clock Prescaler */
556 	volatile uint8_t TWCP;
557 	volatile uint8_t reserved2;
558 	/* 0x004: TWD Timer 0 */
559 	volatile uint16_t TWDT0;
560 	/* 0x006: TWDT0 Control and Status */
561 	volatile uint8_t T0CSR;
562 	volatile uint8_t reserved3;
563 	/* 0x008: Watchdog Count */
564 	volatile uint8_t WDCNT;
565 	volatile uint8_t reserved4;
566 	/* 0x00A: Watchdog Service Data Match */
567 	volatile uint8_t WDSDM;
568 	volatile uint8_t reserved5;
569 	/* 0x00C: TWD Timer 0 Counter */
570 	volatile uint16_t TWMT0;
571 	/* 0x00E: Watchdog Counter */
572 	volatile uint8_t TWMWD;
573 	volatile uint8_t reserved6;
574 	/* 0x010: Watchdog Clock Prescaler */
575 	volatile uint8_t WDCP;
576 	volatile uint8_t reserved7;
577 };
578 
579 /* TWD register fields */
580 #define NPCX_TWCFG_LTWCFG                      0
581 #define NPCX_TWCFG_LTWCP                       1
582 #define NPCX_TWCFG_LTWDT0                      2
583 #define NPCX_TWCFG_LWDCNT                      3
584 #define NPCX_TWCFG_WDCT0I                      4
585 #define NPCX_TWCFG_WDSDME                      5
586 #define NPCX_T0CSR_RST                         0
587 #define NPCX_T0CSR_TC                          1
588 #define NPCX_T0CSR_WDLTD                       3
589 #define NPCX_T0CSR_WDRST_STS                   4
590 #define NPCX_T0CSR_WD_RUN                      5
591 #define NPCX_T0CSR_TESDIS                      7
592 
593 /*
594  * Enhanced Serial Peripheral Interface (eSPI) device registers
595  */
596 struct espi_reg {
597 	/* 0x000: eSPI Identification */
598 	volatile uint32_t ESPIID;
599 	/* 0x004: eSPI Configuration */
600 	volatile uint32_t ESPICFG;
601 	/* 0x008: eSPI Status */
602 	volatile uint32_t ESPISTS;
603 	/* 0x00C: eSPI Interrupt Enable */
604 	volatile uint32_t ESPIIE;
605 	/* 0x010: eSPI Wake-Up Enable */
606 	volatile uint32_t ESPIWE;
607 	/* 0x014: Virtual Wire Register Index */
608 	volatile uint32_t VWREGIDX;
609 	/* 0x018: Virtual Wire Register Data */
610 	volatile uint32_t VWREGDATA;
611 	/* 0x01C: OOB Receive Buffer Read Head */
612 	volatile uint32_t OOBRXRDHEAD;
613 	/* 0x020: OOB Transmit Buffer Write Head */
614 	volatile uint32_t OOBTXWRHEAD;
615 	/* 0x024: OOB Channel Control */
616 	volatile uint32_t OOBCTL;
617 	/* 0x028: Flash Receive Buffer Read Head */
618 	volatile uint32_t FLASHRXRDHEAD;
619 	/* 0x02C: Flash Transmit Buffer Write Head */
620 	volatile uint32_t FLASHTXWRHEAD;
621 	volatile uint32_t reserved1;
622 	/* 0x034: Flash Channel Configuration */
623 	volatile uint32_t FLASHCFG;
624 	/* 0x038: Flash Channel Control */
625 	volatile uint32_t FLASHCTL;
626 	/* 0x03C: eSPI Error Status */
627 	volatile uint32_t ESPIERR;
628 	/* 0x040: Peripheral Bus Master Receive Buffer Read Head */
629 	volatile uint32_t PBMRXRDHEAD;
630 	/* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
631 	volatile uint32_t PBMTXWRHEAD;
632 	/* 0x048: Peripheral Channel Configuration */
633 	volatile uint32_t PERCFG;
634 	/* 0x04C: Peripheral Channel Control */
635 	volatile uint32_t PERCTL;
636 	volatile uint32_t reserved2[44];
637 	/* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
638 	volatile uint32_t VWEVSM[10];
639 	volatile uint32_t reserved3[6];
640 	/* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
641 	volatile uint32_t VWEVMS[12];
642 	volatile uint32_t reserved4[99];
643 	/* 0x2FC: Virtual Wire Channel Control */
644 	volatile uint32_t VWCTL;
645 	/* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
646 	volatile uint32_t OOBRXBUF[20];
647 	volatile uint32_t reserved5[12];
648 	/* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
649 	volatile uint32_t OOBTXBUF[20];
650 	volatile uint32_t reserved6[11];
651 	/* 0x3FC: OOB Channel Control used in 'direct' mode */
652 	volatile uint32_t OOBCTL_DIRECT;
653 	/* 0x400 - 443: Flash Receive Buffer 0-16 */
654 	volatile uint32_t FLASHRXBUF[17];
655 	volatile uint32_t reserved7[15];
656 	/* 0x480 - 497: Flash Transmit Buffer 0-5 */
657 	volatile uint32_t FLASHTXBUF[6];
658 	volatile uint32_t reserved8[25];
659 	/* 0x4FC: Flash Channel Control used in 'direct' mode */
660 	volatile uint32_t FLASHCTL_DIRECT;
661 };
662 
663 /* eSPI register fields */
664 #define NPCX_ESPICFG_PCHANEN             0
665 #define NPCX_ESPICFG_VWCHANEN            1
666 #define NPCX_ESPICFG_OOBCHANEN           2
667 #define NPCX_ESPICFG_FLASHCHANEN         3
668 #define NPCX_ESPICFG_HPCHANEN            4
669 #define NPCX_ESPICFG_HVWCHANEN           5
670 #define NPCX_ESPICFG_HOOBCHANEN          6
671 #define NPCX_ESPICFG_HFLASHCHANEN        7
672 #define NPCX_ESPICFG_CHANS_FIELD         FIELD(0, 4)
673 #define NPCX_ESPICFG_HCHANS_FIELD        FIELD(4, 4)
674 #define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 9)
675 #define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 12)
676 #define NPCX_ESPICFG_PCCHN_SUPP          24
677 #define NPCX_ESPICFG_VWCHN_SUPP          25
678 #define NPCX_ESPICFG_OOBCHN_SUPP         26
679 #define NPCX_ESPICFG_FLASHCHN_SUPP       27
680 #define NPCX_ESPIIE_IBRSTIE              0
681 #define NPCX_ESPIIE_CFGUPDIE             1
682 #define NPCX_ESPIIE_BERRIE               2
683 #define NPCX_ESPIIE_OOBRXIE              3
684 #define NPCX_ESPIIE_FLASHRXIE            4
685 #define NPCX_ESPIIE_SFLASHRDIE           5
686 #define NPCX_ESPIIE_PERACCIE             6
687 #define NPCX_ESPIIE_DFRDIE               7
688 #define NPCX_ESPIIE_VWUPDIE              8
689 #define NPCX_ESPIIE_ESPIRSTIE            9
690 #define NPCX_ESPIIE_PLTRSTIE             10
691 #define NPCX_ESPIIE_AMERRIE              15
692 #define NPCX_ESPIIE_AMDONEIE             16
693 #define NPCX_ESPIIE_BMTXDONEIE           19
694 #define NPCX_ESPIIE_PBMRXIE              20
695 #define NPCX_ESPIIE_PMSGRXIE             21
696 #define NPCX_ESPIIE_BMBURSTERRIE         22
697 #define NPCX_ESPIIE_BMBURSTDONEIE        23
698 #define NPCX_ESPIWE_IBRSTWE              0
699 #define NPCX_ESPIWE_CFGUPDWE             1
700 #define NPCX_ESPIWE_BERRWE               2
701 #define NPCX_ESPIWE_OOBRXWE              3
702 #define NPCX_ESPIWE_FLASHRXWE            4
703 #define NPCX_ESPIWE_PERACCWE             6
704 #define NPCX_ESPIWE_DFRDWE               7
705 #define NPCX_ESPIWE_VWUPDWE              8
706 #define NPCX_ESPIWE_ESPIRSTWE            9
707 #define NPCX_ESPIWE_PBMRXWE              20
708 #define NPCX_ESPIWE_PMSGRXWE             21
709 #define NPCX_ESPISTS_IBRST               0
710 #define NPCX_ESPISTS_CFGUPD              1
711 #define NPCX_ESPISTS_BERR                2
712 #define NPCX_ESPISTS_OOBRX               3
713 #define NPCX_ESPISTS_FLASHRX             4
714 #define NPCX_ESPISTS_PERACC              6
715 #define NPCX_ESPISTS_DFRD                7
716 #define NPCX_ESPISTS_VWUPD               8
717 #define NPCX_ESPISTS_ESPIRST             9
718 #define NPCX_ESPISTS_PLTRST              10
719 #define NPCX_ESPISTS_AMERR               15
720 #define NPCX_ESPISTS_AMDONE              16
721 #define NPCX_ESPISTS_VWUPDW              17
722 #define NPCX_ESPISTS_BMTXDONE            19
723 #define NPCX_ESPISTS_PBMRX               20
724 #define NPCX_ESPISTS_PMSGRX              21
725 #define NPCX_ESPISTS_BMBURSTERR          22
726 #define NPCX_ESPISTS_BMBURSTDONE         23
727 #define NPCX_ESPISTS_ESPIRST_LVL         24
728 #define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
729 #define NPCX_VWEVMS_VALID                FIELD(4, 4)
730 #define NPCX_VWEVMS_IE                   18
731 #define NPCX_VWEVMS_WE                   20
732 #define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
733 #define NPCX_VWEVSM_VALID                FIELD(4, 4)
734 #define NPCX_VWEVSM_BIT_VALID(n)         (4+n)
735 #define NPCX_VWEVSM_HW_WIRE              FIELD(24, 4)
736 #define NPCX_OOBCTL_OOB_FREE             0
737 #define NPCX_OOBCTL_OOB_AVAIL            1
738 #define NPCX_OOBCTL_RSTBUFHEADS          2
739 #define NPCX_OOBCTL_OOBPLSIZE            FIELD(10, 3)
740 #define NPCX_FLASHCFG_FLASHBLERSSIZE     FIELD(7, 3)
741 #define NPCX_FLASHCFG_FLASHPLSIZE        FIELD(10, 3)
742 #define NPCX_FLASHCFG_FLASHREQSIZE       FIELD(13, 3)
743 #define NPCX_FLASHCTL_FLASH_NP_FREE      0
744 #define NPCX_FLASHCTL_FLASH_TX_AVAIL     1
745 #define NPCX_FLASHCTL_STRPHDR            2
746 #define NPCX_FLASHCTL_DMATHRESH          FIELD(3, 2)
747 #define NPCX_FLASHCTL_AMTSIZE            FIELD(5, 8)
748 #define NPCX_FLASHCTL_RSTBUFHEADS        13
749 #define NPCX_FLASHCTL_CRCEN              14
750 #define NPCX_FLASHCTL_CHKSUMSEL          15
751 #define NPCX_FLASHCTL_AMTEN              16
752 
753 /*
754  * Mobile System Wake-Up Control (MSWC) device registers
755  */
756 struct mswc_reg {
757 	/* 0x000: MSWC Control Status 1 */
758 	volatile uint8_t MSWCTL1;
759 	volatile uint8_t reserved1;
760 	/* 0x002: MSWC Control Status 2 */
761 	volatile uint8_t MSWCTL2;
762 	volatile uint8_t reserved2[5];
763 	/* 0x008: Host Configuration Base Address Low */
764 	volatile uint8_t HCBAL;
765 	volatile uint8_t reserved3;
766 	/* 0x00A: Host Configuration Base Address High */
767 	volatile uint8_t HCBAH;
768 	volatile uint8_t reserved4;
769 	/* 0X00C: MSWC INTERRUPT ENABLE 2 */
770 	volatile uint8_t MSIEN2;
771 	volatile uint8_t reserved5;
772 	/* 0x00E: MSWC Host Event Status 0 */
773 	volatile uint8_t MSHES0;
774 	volatile uint8_t reserved6;
775 	/* 0x010: MSWC Host Event Interrupt Enable */
776 	volatile uint8_t MSHEIE0;
777 	volatile uint8_t reserved7;
778 	/* 0x012: Host Control */
779 	volatile uint8_t HOST_CTL;
780 	volatile uint8_t reserved8;
781 	/* 0x014: SMI Pulse Length */
782 	volatile uint8_t SMIP_LEN;
783 	volatile uint8_t reserved9;
784 	/* 0x016: SCI Pulse Length */
785 	volatile uint8_t SCIP_LEN;
786 	volatile uint8_t reserved10[5];
787 	/* 0x01C: SRID Core Access */
788 	volatile uint8_t SRID_CR;
789 	volatile uint8_t reserved11[3];
790 	/* 0x020: SID Core Access */
791 	volatile uint8_t SID_CR;
792 	volatile uint8_t reserved12;
793 	/* 0x022: DEVICE_ID Core Access */
794 	volatile uint8_t DEVICE_ID_CR;
795 	volatile uint8_t reserved13[5];
796 	/* 0x028: Chip Revision Core Access */
797 	volatile uint8_t CHPREV_CR;
798 	volatile uint8_t reserved14[5];
799 	/* 0x02E: Virtual Wire Sleep States */
800 	volatile uint8_t VW_SLPST1;
801 	volatile uint8_t reserved15;
802 };
803 
804 /* MSWC register fields */
805 #define NPCX_MSWCTL1_HRSTOB              0
806 #define NPCS_MSWCTL1_HWPRON              1
807 #define NPCX_MSWCTL1_PLTRST_ACT          2
808 #define NPCX_MSWCTL1_VHCFGA              3
809 #define NPCX_MSWCTL1_HCFGLK              4
810 #define NPCX_MSWCTL1_PWROFFB             6
811 #define NPCX_MSWCTL1_A20MB               7
812 
813 /*
814  * Shared Memory (SHM) device registers
815  */
816 struct shm_reg {
817 	/* 0x000: Shared Memory Core Status */
818 	volatile uint8_t SMC_STS;
819 	/* 0x001: Shared Memory Core Control */
820 	volatile uint8_t SMC_CTL;
821 	/* 0x002: Shared Memory Host Control */
822 	volatile uint8_t SHM_CTL;
823 	volatile uint8_t reserved1[2];
824 	/* 0x005: Indirect Memory Access Window Size */
825 	volatile uint8_t IMA_WIN_SIZE;
826 	volatile uint8_t reserved2;
827 	/* 0x007: Shared Access Windows Size */
828 	volatile uint8_t WIN_SIZE;
829 	/* 0x008: Shared Access Window 1, Semaphore */
830 	volatile uint8_t SHAW1_SEM;
831 	/* 0x009: Shared Access Window 2, Semaphore */
832 	volatile uint8_t SHAW2_SEM;
833 	volatile uint8_t reserved3;
834 	/* 0x00B: Indirect Memory Access, Semaphore */
835 	volatile uint8_t IMA_SEM;
836 	volatile uint8_t reserved4[2];
837 	/* 0x00E: Shared Memory Configuration */
838 	volatile uint16_t SHCFG;
839 	/* 0x010: Shared Access Window 1 Write Protect */
840 	volatile uint8_t WIN1_WR_PROT;
841 	/* 0x011: Shared Access Window 1 Read Protect */
842 	volatile uint8_t WIN1_RD_PROT;
843 	/* 0x012: Shared Access Window 2 Write Protect */
844 	volatile uint8_t WIN2_WR_PROT;
845 	/* 0x013: Shared Access Window 2 Read Protect */
846 	volatile uint8_t WIN2_RD_PROT;
847 	volatile uint8_t reserved5[2];
848 	/* 0x016: Indirect Memory Access Write Protect */
849 	volatile uint8_t IMA_WR_PROT;
850 	/* 0x017: Indirect Memory Access Read Protect */
851 	volatile uint8_t IMA_RD_PROT;
852 	volatile uint8_t reserved6[8];
853 	/* 0x020: Shared Access Window 1 Base */
854 	volatile uint32_t WIN_BASE1;
855 	/* 0x024: Shared Access Window 2 Base */
856 	volatile uint32_t WIN_BASE2;
857 	volatile uint32_t reserved7;
858 	/* 0x02C: Indirect Memory Access Base */
859 	volatile uint32_t IMA_BASE;
860 	volatile uint8_t reserved8[10];
861 	/* 0x03A: Reset Configuration */
862 	volatile uint8_t RST_CFG;
863 	volatile uint8_t reserved9[5];
864 	/* 0x040: Debug Port 80 Buffered Data */
865 	volatile uint16_t DP80BUF;
866 	/* 0x042: Debug Port 80 Status */
867 	volatile uint8_t DP80STS;
868 	volatile uint8_t reserved10;
869 	/* 0x044: Debug Port 80 Control */
870 	volatile uint8_t DP80CTL;
871 	volatile uint8_t reserved11[3];
872 	/* 0x048: Host_Offset in Windows 1, 2 Status */
873 	volatile uint8_t HOFS_STS;
874 	/* 0x049: Host_Offset in Windows 1, 2 Control */
875 	volatile uint8_t HOFS_CTL;
876 	/* 0x04A: Core_Offset in Window 2 Address */
877 	volatile uint16_t COFS2;
878 	/* 0x04C: Core_Offset in Window 1 Address */
879 	volatile uint16_t COFS1;
880 	volatile uint16_t reserved12;
881 };
882 
883 /* SHM register fields */
884 #define NPCX_SMC_STS_HRERR               0
885 #define NPCX_SMC_STS_HWERR               1
886 #define NPCX_SMC_STS_HSEM1W              4
887 #define NPCX_SMC_STS_HSEM2W              5
888 #define NPCX_SMC_STS_SHM_ACC             6
889 #define NPCX_SMC_CTL_HERR_IE             2
890 #define NPCX_SMC_CTL_HSEM1_IE            3
891 #define NPCX_SMC_CTL_HSEM2_IE            4
892 #define NPCX_SMC_CTL_ACC_IE              5
893 #define NPCX_SMC_CTL_PREF_EN             6
894 #define NPCX_SMC_CTL_HOSTWAIT            7
895 #define NPCX_FLASH_SIZE_STALL_HOST       6
896 #define NPCX_FLASH_SIZE_RD_BURST         7
897 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD   FIELD(0, 4)
898 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD   FIELD(4, 4)
899 #define NPCX_WIN_PROT_RW1L_RP            0
900 #define NPCX_WIN_PROT_RW1L_WP            1
901 #define NPCX_WIN_PROT_RW1H_RP            2
902 #define NPCX_WIN_PROT_RW1H_WP            3
903 #define NPCX_WIN_PROT_RW2L_RP            4
904 #define NPCX_WIN_PROT_RW2L_WP            5
905 #define NPCX_WIN_PROT_RW2H_RP            6
906 #define NPCX_WIN_PROT_RW2H_WP            7
907 #define NPCX_PWIN_SIZEI_RPROT            13
908 #define NPCX_PWIN_SIZEI_WPROT            14
909 #define NPCX_CSEM2                       6
910 #define NPCX_CSEM3                       7
911 #define NPCX_DP80STS_FWR                 5
912 #define NPCX_DP80STS_FNE                 6
913 #define NPCX_DP80STS_FOR                 7
914 #define NPCX_DP80CTL_DP80EN              0
915 #define NPCX_DP80CTL_SYNCEN              1
916 #define NPCX_DP80CTL_ADV                 2
917 #define NPCX_DP80CTL_RAA                 3
918 #define NPCX_DP80CTL_RFIFO               4
919 #define NPCX_DP80CTL_CIEN                5
920 #define NPCX_DP80CTL_DP80_HF_CFG         7
921 
922 /*
923  * Keyboard and Mouse Controller (KBC) device registers
924  */
925 struct kbc_reg {
926 	/* 0x000h: Host Interface Control */
927 	volatile uint8_t HICTRL;
928 	volatile uint8_t reserved1;
929 	/* 0x002h: Host Interface IRQ Control */
930 	volatile uint8_t HIIRQC;
931 	volatile uint8_t reserved2;
932 	/* 0x004h: Host Interface Keyboard/Mouse Status */
933 	volatile uint8_t HIKMST;
934 	volatile uint8_t reserved3;
935 	/* 0x006h: Host Interface Keyboard Data Out Buffer */
936 	volatile uint8_t HIKDO;
937 	volatile uint8_t reserved4;
938 	/* 0x008h: Host Interface Mouse Data Out Buffer */
939 	volatile uint8_t HIMDO;
940 	volatile uint8_t reserved5;
941 	/* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
942 	volatile uint8_t HIKMDI;
943 	/* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
944 	volatile uint8_t SHIKMDI;
945 };
946 
947 /* KBC register field */
948 #define NPCX_HICTRL_OBFKIE               0
949 #define NPCX_HICTRL_OBFMIE               1
950 #define NPCX_HICTRL_OBECIE               2
951 #define NPCX_HICTRL_IBFCIE               3
952 #define NPCX_HICTRL_PMIHIE               4
953 #define NPCX_HICTRL_PMIOCIE              5
954 #define NPCX_HICTRL_PMICIE               6
955 #define NPCX_HICTRL_FW_OBF               7
956 #define NPCX_HIKMST_OBF                  0
957 #define NPCX_HIKMST_IBF                  1
958 #define NPCX_HIKMST_F0                   2
959 #define NPCX_HIKMST_A2                   3
960 #define NPCX_HIKMST_ST0                  4
961 #define NPCX_HIKMST_ST1                  5
962 #define NPCX_HIKMST_ST2                  6
963 #define NPCX_HIKMST_ST3                  7
964 
965 /*
966  * Power Management Channel (PMCH) device registers
967  */
968 
969 struct pmch_reg {
970 	/* 0x000: Host Interface PM Status */
971 	volatile uint8_t HIPMST;
972 	volatile uint8_t reserved1;
973 	/* 0x002: Host Interface PM Data Out Buffer */
974 	volatile uint8_t HIPMDO;
975 	volatile uint8_t reserved2;
976 	/* 0x004: Host Interface PM Data In Buffer */
977 	volatile uint8_t HIPMDI;
978 	/* 0x005: Host Interface PM Shadow Data In Buffer */
979 	volatile uint8_t SHIPMDI;
980 	/* 0x006: Host Interface PM Data Out Buffer with SCI */
981 	volatile uint8_t HIPMDOC;
982 	volatile uint8_t reserved3;
983 	/* 0x008: Host Interface PM Data Out Buffer with SMI */
984 	volatile uint8_t HIPMDOM;
985 	volatile uint8_t reserved4;
986 	/* 0x00A: Host Interface PM Data In Buffer with SCI */
987 	volatile uint8_t HIPMDIC;
988 	volatile uint8_t reserved5;
989 	/* 0x00C: Host Interface PM Control */
990 	volatile uint8_t HIPMCTL;
991 	/* 0x00D: Host Interface PM Control 2 */
992 	volatile uint8_t HIPMCTL2;
993 	/* 0x00E: Host Interface PM Interrupt Control */
994 	volatile uint8_t HIPMIC;
995 	volatile uint8_t reserved6;
996 	/* 0x010: Host Interface PM Interrupt Enable */
997 	volatile uint8_t HIPMIE;
998 	volatile uint8_t reserved7;
999 };
1000 
1001 /* PMCH register field */
1002 #define NPCX_HIPMIE_SCIE                 1
1003 #define NPCX_HIPMIE_SMIE                 2
1004 #define NPCX_HIPMCTL_IBFIE               0
1005 #define NPCX_HIPMCTL_OBEIE               1
1006 #define NPCX_HIPMCTL_SCIPOL              6
1007 #define NPCX_HIPMST_OBF                  0
1008 #define NPCX_HIPMST_IBF                  1
1009 #define NPCX_HIPMST_F0                   2
1010 #define NPCX_HIPMST_CMD                  3
1011 #define NPCX_HIPMST_ST0                  4
1012 #define NPCX_HIPMST_ST1                  5
1013 #define NPCX_HIPMST_ST2                  6
1014 #define NPCX_HIPMIC_SMIB                 1
1015 #define NPCX_HIPMIC_SCIB                 2
1016 #define NPCX_HIPMIC_SMIPOL               6
1017 
1018 /*
1019  * Core Access to Host (C2H) device registers
1020  */
1021 struct c2h_reg {
1022 	/* 0x000: Indirect Host I/O Address */
1023 	volatile uint16_t IHIOA;
1024 	/* 0x002: Indirect Host Data */
1025 	volatile uint8_t IHD;
1026 	volatile uint8_t reserved1;
1027 	/* 0x004: Lock Host Access */
1028 	volatile uint16_t LKSIOHA;
1029 	/* 0x006: Access Lock Violation */
1030 	volatile uint16_t SIOLV;
1031 	/* 0x008: Core-to-Host Modules Access Enable */
1032 	volatile uint16_t CRSMAE;
1033 	/* 0x00A: Module Control */
1034 	volatile uint8_t SIBCTRL;
1035 	volatile uint8_t reserved3;
1036 };
1037 
1038 /* C2H register fields */
1039 #define NPCX_LKSIOHA_LKCFG               0
1040 #define NPCX_LKSIOHA_LKSPHA              2
1041 #define NPCX_LKSIOHA_LKHIKBD             11
1042 #define NPCX_CRSMAE_CFGAE                0
1043 #define NPCX_CRSMAE_HIKBDAE              11
1044 #define NPCX_SIOLV_SPLV                  2
1045 #define NPCX_SIBCTRL_CSAE                0
1046 #define NPCX_SIBCTRL_CSRD                1
1047 #define NPCX_SIBCTRL_CSWR                2
1048 
1049 /*
1050  * SMBUS (SMB) device registers
1051  */
1052 struct smb_reg {
1053 	/* 0x000: SMB Serial Data */
1054 	volatile uint8_t SMBSDA;
1055 	volatile uint8_t reserved1;
1056 	/* 0x002: SMB Status */
1057 	volatile uint8_t SMBST;
1058 	volatile uint8_t reserved2;
1059 	/* 0x004: SMB Control Status */
1060 	volatile uint8_t SMBCST;
1061 	volatile uint8_t reserved3;
1062 	/* 0x006: SMB Control 1 */
1063 	volatile uint8_t SMBCTL1;
1064 	volatile uint8_t reserved4;
1065 	/* 0x008: SMB Own Address */
1066 	volatile uint8_t SMBADDR1;
1067 	volatile uint8_t reserved5;
1068 	/* 0x00A: SMB Control 2 */
1069 	volatile uint8_t SMBCTL2;
1070 	volatile uint8_t reserved6;
1071 	/* 0x00C: SMB Own Address */
1072 	volatile uint8_t SMBADDR2;
1073 	volatile uint8_t reserved7;
1074 	/* 0x00E: SMB Control 3 */
1075 	volatile uint8_t SMBCTL3;
1076 	/* 0x00F: SMB Bus Timeout */
1077 	volatile uint8_t SMBT_OUT;
1078 	/* 0x010: SMB Own Address 3 */
1079 	volatile uint8_t SMBADDR3;
1080 	/* 0x011: SMB Own Address 7 */
1081 	volatile uint8_t SMBADDR7;
1082 	/* 0x012: SMB Own Address 4 */
1083 	volatile uint8_t SMBADDR4;
1084 	/* 0x013: SMB Own Address 8 */
1085 	volatile uint8_t SMBADDR8;
1086 	/* 0x014: SMB Own Address 5 */
1087 	volatile uint8_t SMBADDR5;
1088 	volatile uint8_t reserved8;
1089 	/* 0x016: SMB Own Address 6 */
1090 	volatile uint8_t SMBADDR6;
1091 	volatile uint8_t reserved9;
1092 	/* 0x018: SMB Control Status 2 */
1093 	volatile uint8_t SMBCST2;
1094 	/* 0x019: SMB Control Status 3 */
1095 	volatile uint8_t SMBCST3;
1096 	/* 0x01A: SMB Control 4 */
1097 	volatile uint8_t SMBCTL4;
1098 	volatile uint8_t reserved10;
1099 	/* 0x01C: SMB SCL Low Time */
1100 	volatile uint8_t SMBSCLLT;
1101 	/* 0x01D: SMB FIFO Control */
1102 	volatile uint8_t SMBFIF_CTL;
1103 	/* 0x01E: SMB SCL High Time */
1104 	volatile uint8_t SMBSCLHT;
1105 	volatile uint8_t reserved11;
1106 };
1107 
1108 /*
1109  * SMBUS (SMB) FIFO device registers
1110  */
1111 struct smb_fifo_reg {
1112 	/* 0x000: SMB Serial Data */
1113 	volatile uint8_t SMBSDA;
1114 	volatile uint8_t reserved1;
1115 	/* 0x002: SMB Status */
1116 	volatile uint8_t SMBST;
1117 	volatile uint8_t reserved2;
1118 	/* 0x004: SMB Control Status */
1119 	volatile uint8_t SMBCST;
1120 	volatile uint8_t reserved3;
1121 	/* 0x006: SMB Control 1 */
1122 	volatile uint8_t SMBCTL1;
1123 	volatile uint8_t reserved4;
1124 	/* 0x008: SMB Own Address */
1125 	volatile uint8_t SMBADDR1;
1126 	volatile uint8_t reserved5;
1127 	/* 0x00A: SMB Control 2 */
1128 	volatile uint8_t SMBCTL2;
1129 	volatile uint8_t reserved6;
1130 	/* 0x00C: SMB Own Address */
1131 	volatile uint8_t SMBADDR2;
1132 	volatile uint8_t reserved7;
1133 	/* 0x00E: SMB Control 3 */
1134 	volatile uint8_t SMBCTL3;
1135 	/* 0x00F: SMB Bus Timeout */
1136 	volatile uint8_t SMBT_OUT;
1137 	/* 0x010: SMB FIFO Control */
1138 	volatile uint8_t SMBFIF_CTS;
1139 	volatile uint8_t reserved8;
1140 	/* 0x012: SMB Tx-FIFO Control */
1141 	volatile uint8_t SMBTXF_CTL;
1142 	volatile uint8_t reserved9;
1143 	/* 0x014: SMB Bus Timeout */
1144 	volatile uint8_t SMB_T_OUT;
1145 	volatile uint8_t reserved10[3];
1146 	/* 0x018: SMB Control Status 2 */
1147 	volatile uint8_t SMBCST2;
1148 	/* 0x019: SMB Control Status 3 */
1149 	volatile uint8_t SMBCST3;
1150 	/* 0x01A: SMB Tx-FIFO Status */
1151 	volatile uint8_t SMBTXF_STS;
1152 	volatile uint8_t reserved11;
1153 	/* 0x01C: SMB Rx-FIFO Status */
1154 	volatile uint8_t SMBRXF_STS;
1155 	volatile uint8_t reserved12;
1156 	/* 0x01E: SMB Rx-FIFO Contro */
1157 	volatile uint8_t SMBRXF_CTL;
1158 	volatile uint8_t reserved13;
1159 };
1160 
1161 /* SMB register fields */
1162 #define NPCX_SMBST_XMIT                  0
1163 #define NPCX_SMBST_MASTER                1
1164 #define NPCX_SMBST_NMATCH                2
1165 #define NPCX_SMBST_STASTR                3
1166 #define NPCX_SMBST_NEGACK                4
1167 #define NPCX_SMBST_BER                   5
1168 #define NPCX_SMBST_SDAST                 6
1169 #define NPCX_SMBST_SLVSTP                7
1170 #define NPCX_SMBCST_BUSY                 0
1171 #define NPCX_SMBCST_BB                   1
1172 #define NPCX_SMBCST_MATCH                2
1173 #define NPCX_SMBCST_GCMATCH              3
1174 #define NPCX_SMBCST_TSDA                 4
1175 #define NPCX_SMBCST_TGSCL                5
1176 #define NPCX_SMBCST_MATCHAF              6
1177 #define NPCX_SMBCST_ARPMATCH             7
1178 #define NPCX_SMBCST2_MATCHA1F            0
1179 #define NPCX_SMBCST2_MATCHA2F            1
1180 #define NPCX_SMBCST2_MATCHA3F            2
1181 #define NPCX_SMBCST2_MATCHA4F            3
1182 #define NPCX_SMBCST2_MATCHA5F            4
1183 #define NPCX_SMBCST2_MATCHA6F            5
1184 #define NPCX_SMBCST2_MATCHA7F            6
1185 #define NPCX_SMBCST2_INTSTS              7
1186 #define NPCX_SMBCST3_MATCHA8F            0
1187 #define NPCX_SMBCST3_MATCHA9F            1
1188 #define NPCX_SMBCST3_MATCHA10F           2
1189 #define NPCX_SMBCTL1_START               0
1190 #define NPCX_SMBCTL1_STOP                1
1191 #define NPCX_SMBCTL1_INTEN               2
1192 #define NPCX_SMBCTL1_ACK                 4
1193 #define NPCX_SMBCTL1_GCMEN               5
1194 #define NPCX_SMBCTL1_NMINTE              6
1195 #define NPCX_SMBCTL1_STASTRE             7
1196 #define NPCX_SMBCTL2_ENABLE              0
1197 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD     FIELD(1, 7)
1198 #define NPCX_SMBCTL3_ARPMEN              2
1199 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD     FIELD(0, 2)
1200 #define NPCX_SMBCTL3_IDL_START           3
1201 #define NPCX_SMBCTL3_400K                4
1202 #define NPCX_SMBCTL3_BNK_SEL             5
1203 #define NPCX_SMBCTL3_SDA_LVL             6
1204 #define NPCX_SMBCTL3_SCL_LVL             7
1205 #define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
1206 #define NPCX_SMBCTL4_LVL_WE              7
1207 #define NPCX_SMBADDR1_SAEN               7
1208 #define NPCX_SMBADDR2_SAEN               7
1209 #define NPCX_SMBADDR3_SAEN               7
1210 #define NPCX_SMBADDR4_SAEN               7
1211 #define NPCX_SMBADDR5_SAEN               7
1212 #define NPCX_SMBADDR6_SAEN               7
1213 #define NPCX_SMBADDR7_SAEN               7
1214 #define NPCX_SMBADDR8_SAEN               7
1215 #define NPCX_SMBSEL_SMB4SEL              4
1216 #define NPCX_SMBSEL_SMB5SEL              5
1217 #define NPCX_SMBSEL_SMB6SEL              6
1218 #define NPCX_SMBFIF_CTS_RXF_TXE          1
1219 #define NPCX_SMBFIF_CTS_CLR_FIFO         6
1220 #define NPCX_SMBFIF_CTL_FIFO_EN          4
1221 #define NPCX_SMBRXF_STS_RX_THST          6
1222 
1223 /* RX FIFO threshold */
1224 #define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
1225 #define NPCX_SMBRXF_CTL_LAST             7
1226 
1227 /*
1228  * Internal 32-bit Timer (ITIM32) device registers
1229  */
1230 struct itim32_reg {
1231 	volatile uint8_t reserved1;
1232 	/* 0x001: Internal 32-bit Timer Prescaler */
1233 	volatile uint8_t ITPRE32;
1234 	volatile uint8_t reserved2[2];
1235 	/* 0x004: Internal 32-bit Timer Control and Status */
1236 	volatile uint8_t ITCTS32;
1237 	volatile uint8_t reserved3[3];
1238 	/* 0x008: Internal 32-Bit Timer Counter */
1239 	volatile uint32_t ITCNT32;
1240 };
1241 
1242 /*
1243  * Internal 64-bit Timer (ITIM54) device registers
1244  */
1245 struct itim64_reg {
1246 	volatile uint8_t reserved1;
1247 	/* 0x001: Internal 64-bit Timer Prescaler */
1248 	volatile uint8_t ITPRE64;
1249 	volatile uint8_t reserved2[2];
1250 	/* 0x004: Internal 64-bit Timer Control and Status */
1251 	volatile uint8_t ITCTS64;
1252 	volatile uint8_t reserved3[3];
1253 	/* 0x008: Internal 32-Bit Timer Counter */
1254 	volatile uint32_t ITCNT64L;
1255 	/* 0x00C: Internal 32-Bit Timer Counter */
1256 	volatile uint32_t ITCNT64H;
1257 };
1258 
1259 /* ITIM register fields */
1260 #define NPCX_ITCTSXX_TO_STS              0
1261 #define NPCX_ITCTSXX_TO_IE               2
1262 #define NPCX_ITCTSXX_TO_WUE              3
1263 #define NPCX_ITCTSXX_CKSEL               4
1264 #define NPCX_ITCTSXX_ITEN                7
1265 
1266 /*
1267  * Tachometer (TACH) Sensor device registers
1268  */
1269 struct tach_reg {
1270 	/* 0x000: Timer/Counter 1 */
1271 	volatile uint16_t TCNT1;
1272 	/* 0x002: Reload/Capture A */
1273 	volatile uint16_t TCRA;
1274 	/* 0x004: Reload/Capture B */
1275 	volatile uint16_t TCRB;
1276 	/* 0x006: Timer/Counter 2 */
1277 	volatile uint16_t TCNT2;
1278 	/* 0x008: Clock Prescaler */
1279 	volatile uint8_t TPRSC;
1280 	volatile uint8_t reserved1;
1281 	/* 0x00A: Clock Unit Control */
1282 	volatile uint8_t TCKC;
1283 	volatile uint8_t reserved2;
1284 	/* 0x00C: Timer Mode Control */
1285 	volatile uint8_t TMCTRL;
1286 	volatile uint8_t reserved3;
1287 	/* 0x00E: Timer Event Control */
1288 	volatile uint8_t TECTRL;
1289 	volatile uint8_t reserved4;
1290 	/* 0x010: Timer Event Clear */
1291 	volatile uint8_t TECLR;
1292 	volatile uint8_t reserved5;
1293 	/* 0x012: Timer Interrupt Enable */
1294 	volatile uint8_t TIEN;
1295 	volatile uint8_t reserved6;
1296 	/* 0x014: Compare A */
1297 	volatile uint16_t TCPA;
1298 	/* 0x016: Compare B */
1299 	volatile uint16_t TCPB;
1300 	/* 0x018: Compare Configuration */
1301 	volatile uint8_t TCPCFG;
1302 	volatile uint8_t reserved7;
1303 	/* 0x01A: Timer Wake-Up Enablen */
1304 	volatile uint8_t TWUEN;
1305 	volatile uint8_t reserved8;
1306 	/* 0x01C: Timer Configuration */
1307 	volatile uint8_t TCFG;
1308 	volatile uint8_t reserved9;
1309 };
1310 
1311 /* TACH register fields */
1312 #define NPCX_TCKC_LOW_PWR                7
1313 #define NPCX_TCKC_PLS_ACC_CLK            6
1314 #define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
1315 #define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
1316 #define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
1317 #define NPCX_TMCTRL_TAEN                 5
1318 #define NPCX_TMCTRL_TBEN                 6
1319 #define NPCX_TMCTRL_TAEDG                3
1320 #define NPCX_TMCTRL_TBEDG                4
1321 #define NPCX_TCFG_TADBEN                 6
1322 #define NPCX_TCFG_TBDBEN                 7
1323 #define NPCX_TECTRL_TAPND                0
1324 #define NPCX_TECTRL_TBPND                1
1325 #define NPCX_TECTRL_TCPND                2
1326 #define NPCX_TECTRL_TDPND                3
1327 #define NPCX_TECLR_TACLR                 0
1328 #define NPCX_TECLR_TBCLR                 1
1329 #define NPCX_TECLR_TCCLR                 2
1330 #define NPCX_TECLR_TDCLR                 3
1331 #define NPCX_TIEN_TAIEN                  0
1332 #define NPCX_TIEN_TBIEN                  1
1333 #define NPCX_TIEN_TCIEN                  2
1334 #define NPCX_TIEN_TDIEN                  3
1335 #define NPCX_TWUEN_TAWEN                 0
1336 #define NPCX_TWUEN_TBWEN                 1
1337 #define NPCX_TWUEN_TCWEN                 2
1338 #define NPCX_TWUEN_TDWEN                 3
1339 
1340 /* Debug Interface registers */
1341 struct dbg_reg {
1342 	/* 0x000: Debug Control */
1343 	volatile uint8_t DBGCTRL;
1344 	volatile uint8_t reserved1;
1345 	/* 0x002: Debug Freeze Enable 1 */
1346 	volatile uint8_t DBGFRZEN1;
1347 	/* 0x003: Debug Freeze Enable 2 */
1348 	volatile uint8_t DBGFRZEN2;
1349 	/* 0x004: Debug Freeze Enable 3 */
1350 	volatile uint8_t DBGFRZEN3;
1351 	/* 0x005: Debug Freeze Enable 4 */
1352 	volatile uint8_t DBGFRZEN4;
1353 };
1354 /* Debug Interface registers fields */
1355 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
1356 
1357 /* PS/2 Interface registers */
1358 struct ps2_reg {
1359 	/* 0x000: PS/2 Data */
1360 	volatile uint8_t PSDAT;
1361 	volatile uint8_t reserved1;
1362 	/* 0x002: PS/2 Status */
1363 	volatile uint8_t PSTAT;
1364 	volatile uint8_t reserved2;
1365 	/* 0x004: PS/2 Control */
1366 	volatile uint8_t PSCON;
1367 	volatile uint8_t reserved3;
1368 	/* 0x006: PS/2 Output Signal */
1369 	volatile uint8_t PSOSIG;
1370 	volatile uint8_t reserved4;
1371 	/* 0x008: PS/2 Iutput Signal */
1372 	volatile uint8_t PSISIG;
1373 	volatile uint8_t reserved5;
1374 	/* 0x00A: PS/2 Interrupt Enable */
1375 	volatile uint8_t PSIEN;
1376 	volatile uint8_t reserved6;
1377 };
1378 
1379 /* PS/2 Interface registers fields */
1380 #define NPCX_PSTAT_SOT                   0
1381 #define NPCX_PSTAT_EOT                   1
1382 #define NPCX_PSTAT_PERR                  2
1383 #define NPCX_PSTAT_ACH                   FIELD(3, 3)
1384 #define NPCX_PSTAT_RFERR                 6
1385 
1386 #define NPCX_PSCON_EN                    0
1387 #define NPCX_PSCON_XMT                   1
1388 #define NPCX_PSCON_HDRV                  FIELD(2, 2)
1389 #define NPCX_PSCON_IDB                   FIELD(4, 3)
1390 #define NPCX_PSCON_WPUED                 7
1391 
1392 #define NPCX_PSOSIG_WDAT0                0
1393 #define NPCX_PSOSIG_WDAT1                1
1394 #define NPCX_PSOSIG_WDAT2                2
1395 #define NPCX_PSOSIG_CLK0                 3
1396 #define NPCX_PSOSIG_CLK1                 4
1397 #define NPCX_PSOSIG_CLK2                 5
1398 #define NPCX_PSOSIG_WDAT3                6
1399 #define NPCX_PSOSIG_CLK3                 7
1400 #define NPCX_PSOSIG_CLK(n)               (((n) < 3) ? ((n) + 3) : 7)
1401 #define NPCX_PSOSIG_WDAT(n)              (((n) < 3) ? ((n) + 0) : 6)
1402 #define NPCX_PSOSIG_CLK_MASK_ALL \
1403 					 (BIT(NPCX_PSOSIG_CLK0) | \
1404 					  BIT(NPCX_PSOSIG_CLK1) | \
1405 					  BIT(NPCX_PSOSIG_CLK2) | \
1406 					  BIT(NPCX_PSOSIG_CLK3))
1407 
1408 #define NPCX_PSIEN_SOTIE                 0
1409 #define NPCX_PSIEN_EOTIE                 1
1410 #define NPCX_PSIEN_PS2_WUE               4
1411 #define NPCX_PSIEN_PS2_CLK_SEL           7
1412 
1413 #endif /* _NUVOTON_NPCX_REG_DEF_H */
1414