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Searched refs:MT_DEFAULT_SECURE_STATE (Results 1 – 5 of 5) sorted by relevance

/Zephyr-Core-2.7.6/soc/arm64/arm/fvp_aemv8a/
Dmmu_regions.c14 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
19 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
24 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
/Zephyr-Core-2.7.6/soc/arm64/qemu_cortex_a53/
Dmmu_regions.c17 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
22 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
27 MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
/Zephyr-Core-2.7.6/soc/arm64/nxp_layerscape/ls1046a/
Dmmu_regions.c16 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
21 MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
/Zephyr-Core-2.7.6/include/arch/arm64/
Darm_mmu.h77 #define MT_DEFAULT_SECURE_STATE MT_NS macro
79 #define MT_DEFAULT_SECURE_STATE MT_SECURE macro
/Zephyr-Core-2.7.6/arch/arm64/core/
Dmmu.c644 .attrs = MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE },
650 .attrs = MT_NORMAL | MT_P_RX_U_RX | MT_DEFAULT_SECURE_STATE },
656 .attrs = MT_NORMAL | MT_P_RO_U_RO | MT_DEFAULT_SECURE_STATE },