1 /*
2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _MEC172X_ECIA_H
8 #define _MEC172X_ECIA_H
9
10 #include <stdint.h>
11 #include <stddef.h>
12 #include <devicetree.h>
13
14 #define ECIA_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(ecia))
15
16 #define MCHP_FIRST_GIRQ_NOS 8u
17 #define MCHP_LAST_GIRQ_NOS 26u
18
19 /*
20 * GIRQ22 is not connected to the NVIC. GIRQ22 source wake the PLL from
21 * deep sleep to provide clocks for a data transfer.
22 */
23 #define MCHP_ECIA_GIRQ_CLK_WAKE_ONLY 22u
24
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
28
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
32
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
34
35 /* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */
36 #define MCHP_NVIC_NUM_PRI_BITS 3u
37 #define MCHP_NVIC_PRI_LO_VAL 7u
38
39 /*
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
43 */
44 #define MCHP_NUM_NVIC_REGS 6u
45 #define MCHP_NVIC_SET_EN_BASE 0xe000e100u
46 #define MCHP_NVIC_CLR_EN_BASE 0xe000e180u
47 #define MCHP_NVIC_SET_PEND_BASE 0xe000e200u
48 #define MCHP_NVIC_CLR_PEND_BASE 0xe000e280u
49 #define MCHP_NVIC_ACTIVE_BASE 0xe000e800u
50 #define MCHP_NVIC_PRI_BASE 0xe000e400u
51
52 /*
53 * ECIA registers
54 * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one
55 * set of registers.
56 * For historical reason GIRQ's are numbered starting at 8 in the documentation.
57 * This numbering only affects the ECIA BLOCK_EN_SET, BLOCK_EN_CLR, and
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
59 *
60 * Each GIRQ is composed of 5 32-bit registers.
61 * +00h = GIRQ08 Source containing RW/1C status bits
62 * +04h = Enable Set write 1 to bit(s) to enable the corresponding source(s)
63 * +08h = Read-Only Result = Source AND Enable-Set
64 * +0Ch = Enable Clear write 1 to bit(s) to disable the corresponding source(s)
65 * +14h = Reserved(unused).
66 * +18h = GIRQ09 Source
67 * ...
68 * There are three other registers at offset 0x200, 0x204, and 0x208
69 * 0x200: BLOCK_EN_SET bit == 1 connects bit-wise OR of all GIRQn result
70 * to a NVIC GIRQn input.
71 * bit[8]=GIRQ8, bit[9]=GIRQ9, ..., bit[26]=GIRQ26
72 * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
73 * bits from NVIC GIRQn input.
74 * 0x208: BLOCK_ACTIVE (read-only)
75 * bit[8]=GIRQ8 has at least one source bit enabled and active.
76 * ...
77 * bit[26]=GIRQ26 has at least one source bit enabled and active.
78 * The aggregated (bit-wise OR) of GIRQ08, ..., GIRQ26 are connected to NVIC
79 * external inputs except for GIRQ22. GIRQ22 is a special peripheral clock
80 * wake. If GIRQ22 sources are enabled activity on a source will re-enable the
81 * PLL long enough for a data transfer from the external device. If the data
82 * transfer requires the CPU to be notified the normal peripheral interrupt
83 * will then fire waking the CPU. If no CPU notification was enabled, HW will
84 * disable the PLL once the data transfer completes allowing the SoC to
85 * re-enter deep sleep.
86 * Aggregated GIRQ NVIC mapping:
87 * GIRQ08 -> NVIC 0
88 * GIRQ09 -> NVIC 1
89 * ...
90 * GIRQ21 -> NVIC 13
91 * GIRQ22 No connection to NVIC
92 * GIRQ23 -> NVIC 14
93 * ...
94 * GIRQ26 -> NVIC 17
95 * NVIC 20 and above are direct mode(not aggregated) connections.
96 * Result bits in GIRQ's 13 - 21, and 23 can be directly connected to NVIC
97 * external inputs 20 and above.
98 */
99 #define MCHP_ECIA_BLK_ENSET_OFS 0x200u
100 #define MCHP_ECIA_BLK_ENCLR_OFS 0x204u
101 #define MCHP_ECIA_BLK_ACTIVE_OFS 0x208u
102
103 enum MCHP_GIRQ_IDS {
104 MCHP_GIRQ08_ID = 8,
105 MCHP_GIRQ09_ID,
106 MCHP_GIRQ10_ID,
107 MCHP_GIRQ11_ID,
108 MCHP_GIRQ12_ID,
109 MCHP_GIRQ13_ID,
110 MCHP_GIRQ14_ID,
111 MCHP_GIRQ15_ID,
112 MCHP_GIRQ16_ID,
113 MCHP_GIRQ17_ID,
114 MCHP_GIRQ18_ID,
115 MCHP_GIRQ19_ID,
116 MCHP_GIRQ20_ID,
117 MCHP_GIRQ21_ID,
118 MCHP_GIRQ22_ID,
119 MCHP_GIRQ23_ID,
120 MCHP_GIRQ24_ID,
121 MCHP_GIRQ25_ID,
122 MCHP_GIRQ26_ID,
123 MCHP_GIRQ_ID_MAX,
124 };
125
126 /* zero based index into ECIA_Type GIRQ[] */
127 enum MCHP_GIRQ_INDEX {
128 GIRQ08_IDX = 0,
129 GIRQ09_IDX,
130 GIRQ10_IDX,
131 GIRQ11_IDX,
132 GIRQ12_IDX,
133 GIRQ13_IDX,
134 GIRQ14_IDX,
135 GIRQ15_IDX,
136 GIRQ16_IDX,
137 GIRQ17_IDX,
138 GIRQ18_IDX,
139 GIRQ19_IDX,
140 GIRQ20_IDX,
141 GIRQ21_IDX,
142 GIRQ22_IDX,
143 GIRQ23_IDX,
144 GIRQ24_IDX,
145 GIRQ25_IDX,
146 GIRQ26_IDX,
147 GIRQ_MAX_IDX
148 };
149
150 /* GIRQ08 Source, Enable_Set/Clr, Result registers bit positions */
151 #define MCHP_GPIO_0140_GIRQ_POS 0
152 #define MCHP_GPIO_0141_GIRQ_POS 1
153 #define MCHP_GPIO_0142_GIRQ_POS 2
154 #define MCHP_GPIO_0143_GIRQ_POS 3
155 #define MCHP_GPIO_0144_GIRQ_POS 4
156 #define MCHP_GPIO_0145_GIRQ_POS 5
157 #define MCHP_GPIO_0146_GIRQ_POS 6
158 #define MCHP_GPIO_0147_GIRQ_POS 7
159 #define MCHP_GPIO_0150_GIRQ_POS 8
160 #define MCHP_GPIO_0151_GIRQ_POS 9
161 #define MCHP_GPIO_0152_GIRQ_POS 10
162 #define MCHP_GPIO_0153_GIRQ_POS 11
163 #define MCHP_GPIO_0154_GIRQ_POS 12
164 #define MCHP_GPIO_0155_GIRQ_POS 13
165 #define MCHP_GPIO_0156_GIRQ_POS 14
166 #define MCHP_GPIO_0157_GIRQ_POS 15
167 #define MCHP_GPIO_0160_GIRQ_POS 16
168 #define MCHP_GPIO_0161_GIRQ_POS 17
169 #define MCHP_GPIO_0162_GIRQ_POS 18
170 #define MCHP_GPIO_0165_GIRQ_POS 21
171 #define MCHP_GPIO_0166_GIRQ_POS 22
172 #define MCHP_GPIO_0170_GIRQ_POS 24
173 #define MCHP_GPIO_0171_GIRQ_POS 25
174 #define MCHP_GPIO_0172_GIRQ_POS 26
175 #define MCHP_GPIO_0173_GIRQ_POS 27
176 #define MCHP_GPIO_0174_GIRQ_POS 28
177 #define MCHP_GPIO_0175_GIRQ_POS 29
178
179 #define MCHP_GPIO_0140_GIRQ_BIT BIT(0)
180 #define MCHP_GPIO_0141_GIRQ_BIT BIT(1)
181 #define MCHP_GPIO_0142_GIRQ_BIT BIT(2)
182 #define MCHP_GPIO_0143_GIRQ_BIT BIT(3)
183 #define MCHP_GPIO_0144_GIRQ_BIT BIT(4)
184 #define MCHP_GPIO_0145_GIRQ_BIT BIT(5)
185 #define MCHP_GPIO_0146_GIRQ_BIT BIT(6)
186 #define MCHP_GPIO_0147_GIRQ_BIT BIT(7)
187 #define MCHP_GPIO_0150_GIRQ_BIT BIT(8)
188 #define MCHP_GPIO_0151_GIRQ_BIT BIT(9)
189 #define MCHP_GPIO_0152_GIRQ_BIT BIT(10)
190 #define MCHP_GPIO_0153_GIRQ_BIT BIT(11)
191 #define MCHP_GPIO_0154_GIRQ_BIT BIT(12)
192 #define MCHP_GPIO_0155_GIRQ_BIT BIT(13)
193 #define MCHP_GPIO_0156_GIRQ_BIT BIT(14)
194 #define MCHP_GPIO_0157_GIRQ_BIT BIT(15)
195 #define MCHP_GPIO_0160_GIRQ_BIT BIT(16)
196 #define MCHP_GPIO_0161_GIRQ_BIT BIT(17)
197 #define MCHP_GPIO_0162_GIRQ_BIT BIT(18)
198 #define MCHP_GPIO_0165_GIRQ_BIT BIT(21)
199 #define MCHP_GPIO_0166_GIRQ_BIT BIT(22)
200 #define MCHP_GPIO_0170_GIRQ_BIT BIT(24)
201 #define MCHP_GPIO_0171_GIRQ_BIT BIT(25)
202 #define MCHP_GPIO_0172_GIRQ_BIT BIT(26)
203 #define MCHP_GPIO_0173_GIRQ_BIT BIT(27)
204 #define MCHP_GPIO_0174_GIRQ_BIT BIT(28)
205 #define MCHP_GPIO_0175_GIRQ_BIT BIT(29)
206 #define MCHP_GPIO_0140_0176_GIRQ_MASK 0x3f67ffffu
207
208 /* GIRQ09 Source, Enable_Set/Clr, Result registers bit positions */
209 #define MCHP_GPIO_0100_GIRQ_POS 0
210 #define MCHP_GPIO_0101_GIRQ_POS 1
211 #define MCHP_GPIO_0102_GIRQ_POS 2
212 #define MCHP_GPIO_0103_GIRQ_POS 3
213 #define MCHP_GPIO_0104_GIRQ_POS 4
214 #define MCHP_GPIO_0105_GIRQ_POS 5
215 #define MCHP_GPIO_0106_GIRQ_POS 6
216 #define MCHP_GPIO_0107_GIRQ_POS 7
217 #define MCHP_GPIO_0110_GIRQ_POS 8
218 #define MCHP_GPIO_0111_GIRQ_POS 9
219 #define MCHP_GPIO_0112_GIRQ_POS 10
220 #define MCHP_GPIO_0113_GIRQ_POS 11
221 #define MCHP_GPIO_0114_GIRQ_POS 12
222 #define MCHP_GPIO_0115_GIRQ_POS 13
223 #define MCHP_GPIO_0116_GIRQ_POS 14
224 #define MCHP_GPIO_0117_GIRQ_POS 15
225 #define MCHP_GPIO_0120_GIRQ_POS 16
226 #define MCHP_GPIO_0121_GIRQ_POS 17
227 #define MCHP_GPIO_0122_GIRQ_POS 18
228 #define MCHP_GPIO_0123_GIRQ_POS 19
229 #define MCHP_GPIO_0124_GIRQ_POS 20
230 #define MCHP_GPIO_0125_GIRQ_POS 21
231 #define MCHP_GPIO_0126_GIRQ_POS 22
232 #define MCHP_GPIO_0127_GIRQ_POS 23
233 #define MCHP_GPIO_0130_GIRQ_POS 24
234 #define MCHP_GPIO_0131_GIRQ_POS 25
235 #define MCHP_GPIO_0132_GIRQ_POS 26
236 #define MCHP_GPIO_0133_GIRQ_POS 27
237 #define MCHP_GPIO_0134_GIRQ_POS 28
238 #define MCHP_GPIO_0135_GIRQ_POS 29
239
240 #define MCHP_GPIO_0100_GIRQ_BIT BIT(0)
241 #define MCHP_GPIO_0101_GIRQ_BIT BIT(1)
242 #define MCHP_GPIO_0102_GIRQ_BIT BIT(2)
243 #define MCHP_GPIO_0103_GIRQ_BIT BIT(3)
244 #define MCHP_GPIO_0104_GIRQ_BIT BIT(4)
245 #define MCHP_GPIO_0105_GIRQ_BIT BIT(5)
246 #define MCHP_GPIO_0106_GIRQ_BIT BIT(6)
247 #define MCHP_GPIO_0107_GIRQ_BIT BIT(7)
248 #define MCHP_GPIO_0110_GIRQ_BIT BIT(8)
249 #define MCHP_GPIO_0111_GIRQ_BIT BIT(9)
250 #define MCHP_GPIO_0112_GIRQ_BIT BIT(10)
251 #define MCHP_GPIO_0113_GIRQ_BIT BIT(11)
252 #define MCHP_GPIO_0114_GIRQ_BIT BIT(12)
253 #define MCHP_GPIO_0115_GIRQ_BIT BIT(13)
254 #define MCHP_GPIO_0116_GIRQ_BIT BIT(14)
255 #define MCHP_GPIO_0117_GIRQ_BIT BIT(15)
256 #define MCHP_GPIO_0120_GIRQ_BIT BIT(16)
257 #define MCHP_GPIO_0121_GIRQ_BIT BIT(17)
258 #define MCHP_GPIO_0122_GIRQ_BIT BIT(18)
259 #define MCHP_GPIO_0123_GIRQ_BIT BIT(19)
260 #define MCHP_GPIO_0124_GIRQ_BIT BIT(20)
261 #define MCHP_GPIO_0125_GIRQ_BIT BIT(21)
262 #define MCHP_GPIO_0126_GIRQ_BIT BIT(22)
263 #define MCHP_GPIO_0127_GIRQ_BIT BIT(23)
264 #define MCHP_GPIO_0130_GIRQ_BIT BIT(24)
265 #define MCHP_GPIO_0131_GIRQ_BIT BIT(25)
266 #define MCHP_GPIO_0132_GIRQ_BIT BIT(26)
267 #define MCHP_GPIO_0133_GIRQ_BIT BIT(27)
268 #define MCHP_GPIO_0134_GIRQ_BIT BIT(28)
269 #define MCHP_GPIO_0135_GIRQ_BIT BIT(29)
270 #define MCHP_GPIO_0100_0136_GIRQ_MASK 0x3fffffffu
271
272 /* GIRQ10 Source, Enable_Set/Clr, Result registers bit positions */
273 #define MCHP_GPIO_0040_GIRQ_POS 0
274 #define MCHP_GPIO_0041_GIRQ_POS 1
275 #define MCHP_GPIO_0042_GIRQ_POS 2
276 #define MCHP_GPIO_0043_GIRQ_POS 3
277 #define MCHP_GPIO_0044_GIRQ_POS 4
278 #define MCHP_GPIO_0045_GIRQ_POS 5
279 #define MCHP_GPIO_0046_GIRQ_POS 6
280 #define MCHP_GPIO_0047_GIRQ_POS 7
281 #define MCHP_GPIO_0050_GIRQ_POS 8
282 #define MCHP_GPIO_0051_GIRQ_POS 9
283 #define MCHP_GPIO_0052_GIRQ_POS 10
284 #define MCHP_GPIO_0053_GIRQ_POS 11
285 #define MCHP_GPIO_0054_GIRQ_POS 12
286 #define MCHP_GPIO_0055_GIRQ_POS 13
287 #define MCHP_GPIO_0056_GIRQ_POS 14
288 #define MCHP_GPIO_0057_GIRQ_POS 15
289 #define MCHP_GPIO_0060_GIRQ_POS 16
290 #define MCHP_GPIO_0061_GIRQ_POS 17
291 #define MCHP_GPIO_0062_GIRQ_POS 18
292 #define MCHP_GPIO_0063_GIRQ_POS 19
293 #define MCHP_GPIO_0064_GIRQ_POS 20
294 #define MCHP_GPIO_0065_GIRQ_POS 21
295 #define MCHP_GPIO_0066_GIRQ_POS 22
296 #define MCHP_GPIO_0067_GIRQ_POS 23
297 #define MCHP_GPIO_0070_GIRQ_POS 24
298 #define MCHP_GPIO_0071_GIRQ_POS 25
299 #define MCHP_GPIO_0072_GIRQ_POS 26
300 #define MCHP_GPIO_0073_GIRQ_POS 27
301 #define MCHP_GPIO_0074_GIRQ_POS 28
302 #define MCHP_GPIO_0075_GIRQ_POS 29
303 #define MCHP_GPIO_0076_GIRQ_POS 30
304
305 #define MCHP_GPIO_0040_GIRQ_BIT BIT(0)
306 #define MCHP_GPIO_0041_GIRQ_BIT BIT(1)
307 #define MCHP_GPIO_0042_GIRQ_BIT BIT(2)
308 #define MCHP_GPIO_0043_GIRQ_BIT BIT(3)
309 #define MCHP_GPIO_0044_GIRQ_BIT BIT(4)
310 #define MCHP_GPIO_0045_GIRQ_BIT BIT(5)
311 #define MCHP_GPIO_0046_GIRQ_BIT BIT(6)
312 #define MCHP_GPIO_0047_GIRQ_BIT BIT(7)
313 #define MCHP_GPIO_0050_GIRQ_BIT BIT(8)
314 #define MCHP_GPIO_0051_GIRQ_BIT BIT(9)
315 #define MCHP_GPIO_0052_GIRQ_BIT BIT(10)
316 #define MCHP_GPIO_0053_GIRQ_BIT BIT(11)
317 #define MCHP_GPIO_0054_GIRQ_BIT BIT(12)
318 #define MCHP_GPIO_0055_GIRQ_BIT BIT(13)
319 #define MCHP_GPIO_0056_GIRQ_BIT BIT(14)
320 #define MCHP_GPIO_0057_GIRQ_BIT BIT(15)
321 #define MCHP_GPIO_0060_GIRQ_BIT BIT(16)
322 #define MCHP_GPIO_0061_GIRQ_BIT BIT(17)
323 #define MCHP_GPIO_0062_GIRQ_BIT BIT(18)
324 #define MCHP_GPIO_0063_GIRQ_BIT BIT(19)
325 #define MCHP_GPIO_0064_GIRQ_BIT BIT(20)
326 #define MCHP_GPIO_0065_GIRQ_BIT BIT(21)
327 #define MCHP_GPIO_0066_GIRQ_BIT BIT(22)
328 #define MCHP_GPIO_0067_GIRQ_BIT BIT(23)
329 #define MCHP_GPIO_0070_GIRQ_BIT BIT(24)
330 #define MCHP_GPIO_0071_GIRQ_BIT BIT(25)
331 #define MCHP_GPIO_0072_GIRQ_BIT BIT(26)
332 #define MCHP_GPIO_0073_GIRQ_BIT BIT(27)
333 #define MCHP_GPIO_0074_GIRQ_BIT BIT(28)
334 #define MCHP_GPIO_0075_GIRQ_BIT BIT(29)
335 #define MCHP_GPIO_0076_GIRQ_BIT BIT(30)
336 #define MCHP_GPIO_0040_0076_GIRQ_MASK 0x7fffffffu
337
338 /* GIRQ11 Source, Enable_Set/Clr, Result registers bit positions */
339 #define MCHP_GPIO_0000_GIRQ_POS 0
340 #define MCHP_GPIO_0001_GIRQ_POS 1
341 #define MCHP_GPIO_0002_GIRQ_POS 2
342 #define MCHP_GPIO_0003_GIRQ_POS 3
343 #define MCHP_GPIO_0004_GIRQ_POS 4
344 #define MCHP_GPIO_0005_GIRQ_POS 5
345 #define MCHP_GPIO_0006_GIRQ_POS 6
346 #define MCHP_GPIO_0007_GIRQ_POS 7
347 #define MCHP_GPIO_0010_GIRQ_POS 8
348 #define MCHP_GPIO_0011_GIRQ_POS 9
349 #define MCHP_GPIO_0012_GIRQ_POS 10
350 #define MCHP_GPIO_0013_GIRQ_POS 11
351 #define MCHP_GPIO_0014_GIRQ_POS 12
352 #define MCHP_GPIO_0015_GIRQ_POS 13
353 #define MCHP_GPIO_0016_GIRQ_POS 14
354 #define MCHP_GPIO_0017_GIRQ_POS 15
355 #define MCHP_GPIO_0020_GIRQ_POS 16
356 #define MCHP_GPIO_0021_GIRQ_POS 17
357 #define MCHP_GPIO_0022_GIRQ_POS 18
358 #define MCHP_GPIO_0023_GIRQ_POS 19
359 #define MCHP_GPIO_0024_GIRQ_POS 20
360 #define MCHP_GPIO_0025_GIRQ_POS 21
361 #define MCHP_GPIO_0026_GIRQ_POS 22
362 #define MCHP_GPIO_0027_GIRQ_POS 23
363 #define MCHP_GPIO_0030_GIRQ_POS 24
364 #define MCHP_GPIO_0031_GIRQ_POS 25
365 #define MCHP_GPIO_0032_GIRQ_POS 26
366 #define MCHP_GPIO_0033_GIRQ_POS 27
367 #define MCHP_GPIO_0034_GIRQ_POS 28
368 #define MCHP_GPIO_0035_GIRQ_POS 29
369 #define MCHP_GPIO_0036_GIRQ_POS 30
370
371 #define MCHP_GPIO_0000_GIRQ_BIT BIT(0)
372 #define MCHP_GPIO_0001_GIRQ_BIT BIT(1)
373 #define MCHP_GPIO_0002_GIRQ_BIT BIT(2)
374 #define MCHP_GPIO_0003_GIRQ_BIT BIT(3)
375 #define MCHP_GPIO_0004_GIRQ_BIT BIT(4)
376 #define MCHP_GPIO_0005_GIRQ_BIT BIT(5)
377 #define MCHP_GPIO_0006_GIRQ_BIT BIT(6)
378 #define MCHP_GPIO_0007_GIRQ_BIT BIT(7)
379 #define MCHP_GPIO_0010_GIRQ_BIT BIT(8)
380 #define MCHP_GPIO_0011_GIRQ_BIT BIT(9)
381 #define MCHP_GPIO_0012_GIRQ_BIT BIT(10)
382 #define MCHP_GPIO_0013_GIRQ_BIT BIT(11)
383 #define MCHP_GPIO_0014_GIRQ_BIT BIT(12)
384 #define MCHP_GPIO_0015_GIRQ_BIT BIT(13)
385 #define MCHP_GPIO_0016_GIRQ_BIT BIT(14)
386 #define MCHP_GPIO_0017_GIRQ_BIT BIT(15)
387 #define MCHP_GPIO_0020_GIRQ_BIT BIT(16)
388 #define MCHP_GPIO_0021_GIRQ_BIT BIT(17)
389 #define MCHP_GPIO_0022_GIRQ_BIT BIT(18)
390 #define MCHP_GPIO_0023_GIRQ_BIT BIT(19)
391 #define MCHP_GPIO_0024_GIRQ_BIT BIT(20)
392 #define MCHP_GPIO_0025_GIRQ_BIT BIT(21)
393 #define MCHP_GPIO_0026_GIRQ_BIT BIT(22)
394 #define MCHP_GPIO_0027_GIRQ_BIT BIT(23)
395 #define MCHP_GPIO_0030_GIRQ_BIT BIT(24)
396 #define MCHP_GPIO_0031_GIRQ_BIT BIT(25)
397 #define MCHP_GPIO_0032_GIRQ_BIT BIT(26)
398 #define MCHP_GPIO_0033_GIRQ_BIT BIT(27)
399 #define MCHP_GPIO_0034_GIRQ_BIT BIT(28)
400 #define MCHP_GPIO_0035_GIRQ_BIT BIT(29)
401 #define MCHP_GPIO_0036_GIRQ_BIT BIT(30)
402 #define MCHP_GPIO_0000_0036_GIRQ_MASK 0x7fffffffu
403
404 /* GIRQ12 Source, Enable_Set/Clr, Result registers bit positions */
405 #define MCHP_GPIO_0200_GIRQ_POS 0
406 #define MCHP_GPIO_0201_GIRQ_POS 1
407 #define MCHP_GPIO_0202_GIRQ_POS 2
408 #define MCHP_GPIO_0203_GIRQ_POS 3
409 #define MCHP_GPIO_0204_GIRQ_POS 4
410 #define MCHP_GPIO_0205_GIRQ_POS 5
411 #define MCHP_GPIO_0206_GIRQ_POS 6
412 #define MCHP_GPIO_0207_GIRQ_POS 7
413 #define MCHP_GPIO_0210_GIRQ_POS 8
414 #define MCHP_GPIO_0211_GIRQ_POS 9
415 #define MCHP_GPIO_0212_GIRQ_POS 10
416 #define MCHP_GPIO_0213_GIRQ_POS 11
417 #define MCHP_GPIO_0214_GIRQ_POS 12
418 #define MCHP_GPIO_0215_GIRQ_POS 13
419 #define MCHP_GPIO_0216_GIRQ_POS 14
420 #define MCHP_GPIO_0217_GIRQ_POS 15
421 #define MCHP_GPIO_0220_GIRQ_POS 16
422 #define MCHP_GPIO_0221_GIRQ_POS 17
423 #define MCHP_GPIO_0222_GIRQ_POS 18
424 #define MCHP_GPIO_0223_GIRQ_POS 19
425 #define MCHP_GPIO_0224_GIRQ_POS 20
426 #define MCHP_GPIO_0225_GIRQ_POS 21
427 #define MCHP_GPIO_0226_GIRQ_POS 22
428 #define MCHP_GPIO_0227_GIRQ_POS 23
429 #define MCHP_GPIO_0230_GIRQ_POS 24
430 #define MCHP_GPIO_0231_GIRQ_POS 25
431 #define MCHP_GPIO_0232_GIRQ_POS 26
432 #define MCHP_GPIO_0233_GIRQ_POS 27
433 #define MCHP_GPIO_0234_GIRQ_POS 28
434 #define MCHP_GPIO_0235_GIRQ_POS 29
435 #define MCHP_GPIO_0236_GIRQ_POS 30
436
437 #define MCHP_GPIO_0200_GIRQ_BIT BIT(0)
438 #define MCHP_GPIO_0201_GIRQ_BIT BIT(1)
439 #define MCHP_GPIO_0202_GIRQ_BIT BIT(2)
440 #define MCHP_GPIO_0203_GIRQ_BIT BIT(3)
441 #define MCHP_GPIO_0204_GIRQ_BIT BIT(4)
442 #define MCHP_GPIO_0205_GIRQ_BIT BIT(5)
443 #define MCHP_GPIO_0206_GIRQ_BIT BIT(6)
444 #define MCHP_GPIO_0207_GIRQ_BIT BIT(7)
445 #define MCHP_GPIO_0210_GIRQ_BIT BIT(8)
446 #define MCHP_GPIO_0211_GIRQ_BIT BIT(9)
447 #define MCHP_GPIO_0212_GIRQ_BIT BIT(10)
448 #define MCHP_GPIO_0213_GIRQ_BIT BIT(11)
449 #define MCHP_GPIO_0214_GIRQ_BIT BIT(12)
450 #define MCHP_GPIO_0215_GIRQ_BIT BIT(13)
451 #define MCHP_GPIO_0216_GIRQ_BIT BIT(14)
452 #define MCHP_GPIO_0217_GIRQ_BIT BIT(15)
453 #define MCHP_GPIO_0220_GIRQ_BIT BIT(16)
454 #define MCHP_GPIO_0221_GIRQ_BIT BIT(17)
455 #define MCHP_GPIO_0222_GIRQ_BIT BIT(18)
456 #define MCHP_GPIO_0223_GIRQ_BIT BIT(19)
457 #define MCHP_GPIO_0224_GIRQ_BIT BIT(20)
458 #define MCHP_GPIO_0225_GIRQ_BIT BIT(21)
459 #define MCHP_GPIO_0226_GIRQ_BIT BIT(22)
460 #define MCHP_GPIO_0227_GIRQ_BIT BIT(23)
461 #define MCHP_GPIO_0230_GIRQ_BIT BIT(24)
462 #define MCHP_GPIO_0231_GIRQ_BIT BIT(25)
463 #define MCHP_GPIO_0232_GIRQ_BIT BIT(26)
464 #define MCHP_GPIO_0233_GIRQ_BIT BIT(27)
465 #define MCHP_GPIO_0234_GIRQ_BIT BIT(28)
466 #define MCHP_GPIO_0235_GIRQ_BIT BIT(29)
467 #define MCHP_GPIO_0236_GIRQ_BIT BIT(30)
468 #define MCHP_GPIO_0200_0236_GIRQ_MASK 0x7fffffffu
469
470 /* GIRQ13 Source, Enable_Set/Clr, Result registers bit positions */
471 #define MCHP_I2C_SMB_0_GIRQ_POS 0
472 #define MCHP_I2C_SMB_1_GIRQ_POS 1
473 #define MCHP_I2C_SMB_2_GIRQ_POS 2
474 #define MCHP_I2C_SMB_3_GIRQ_POS 3
475 #define MCHP_I2C_SMB_4_GIRQ_POS 4
476
477 #define MCHP_I2C_SMB_0_GIRQ_BIT BIT(0)
478 #define MCHP_I2C_SMB_1_GIRQ_BIT BIT(1)
479 #define MCHP_I2C_SMB_2_GIRQ_BIT BIT(2)
480 #define MCHP_I2C_SMB_3_GIRQ_BIT BIT(3)
481 #define MCHP_I2C_SMB_4_GIRQ_BIT BIT(4)
482 #define MCHP_SMB_I2C_GIRQ_MASK 0x1fu
483
484 #define MCHP_GIRQ13_NVIC_AGGR 5u
485 #define MCHP_GIRQ13_NVIC_DIRECT(bitpos) (20u + (uint32_t)(bitpos))
486
487 /* GIRQ14 Source, Enable_Set/Clr, Result registers bit positions */
488 #define MCHP_DMA_CH00_GIRQ_POS 0
489 #define MCHP_DMA_CH01_GIRQ_POS 1
490 #define MCHP_DMA_CH02_GIRQ_POS 2
491 #define MCHP_DMA_CH03_GIRQ_POS 3
492 #define MCHP_DMA_CH04_GIRQ_POS 4
493 #define MCHP_DMA_CH05_GIRQ_POS 5
494 #define MCHP_DMA_CH06_GIRQ_POS 6
495 #define MCHP_DMA_CH07_GIRQ_POS 7
496 #define MCHP_DMA_CH08_GIRQ_POS 8
497 #define MCHP_DMA_CH09_GIRQ_POS 9
498 #define MCHP_DMA_CH10_GIRQ_POS 10
499 #define MCHP_DMA_CH11_GIRQ_POS 11
500 #define MCHP_DMA_CH12_GIRQ_POS 12
501 #define MCHP_DMA_CH13_GIRQ_POS 13
502 #define MCHP_DMA_CH14_GIRQ_POS 14
503 #define MCHP_DMA_CH15_GIRQ_POS 15
504
505 #define MCHP_DMA_CH00_GIRQ_BIT BIT(0)
506 #define MCHP_DMA_CH01_GIRQ_BIT BIT(1)
507 #define MCHP_DMA_CH02_GIRQ_BIT BIT(2)
508 #define MCHP_DMA_CH03_GIRQ_BIT BIT(3)
509 #define MCHP_DMA_CH04_GIRQ_BIT BIT(4)
510 #define MCHP_DMA_CH05_GIRQ_BIT BIT(5)
511 #define MCHP_DMA_CH06_GIRQ_BIT BIT(6)
512 #define MCHP_DMA_CH07_GIRQ_BIT BIT(7)
513 #define MCHP_DMA_CH08_GIRQ_BIT BIT(8)
514 #define MCHP_DMA_CH09_GIRQ_BIT BIT(9)
515 #define MCHP_DMA_CH10_GIRQ_BIT BIT(10)
516 #define MCHP_DMA_CH11_GIRQ_BIT BIT(11)
517 #define MCHP_DMA_CH12_GIRQ_BIT BIT(12)
518 #define MCHP_DMA_CH13_GIRQ_BIT BIT(13)
519 #define MCHP_DMA_CH14_GIRQ_BIT BIT(14)
520 #define MCHP_DMA_CH15_GIRQ_BIT BIT(15)
521 #define MCHP_DMA_GIRQ_MASK 0xffffu
522
523 #define MCHP_GIRQ14_NVIC_AGGR 6u
524 #define MCHP_GIRQ14_NVIC_DIRECT(bitpos) (24u + (uint32_t)(bitpos))
525
526 /* GIRQ15 Source, Enable_Set/Clr, Result registers bit positions */
527 #define MCHP_UART_0_GIRQ_POS 0
528 #define MCHP_UART_1_GIRQ_POS 1
529 #define MCHP_EMI_0_GIRQ_POS 2
530 #define MCHP_EMI_1_GIRQ_POS 3
531 #define MCHP_EMI_2_GIRQ_POS 4
532 #define MCHP_ACPI_EC_0_IBF_GIRQ_POS 5
533 #define MCHP_ACPI_EC_0_OBE_GIRQ_POS 6
534 #define MCHP_ACPI_EC_1_IBF_GIRQ_POS 7
535 #define MCHP_ACPI_EC_1_OBE_GIRQ_POS 8
536 #define MCHP_ACPI_EC_2_IBF_GIRQ_POS 9
537 #define MCHP_ACPI_EC_2_OBE_GIRQ_POS 10
538 #define MCHP_ACPI_EC_3_IBF_GIRQ_POS 11
539 #define MCHP_ACPI_EC_3_OBE_GIRQ_POS 12
540 #define MCHP_ACPI_EC_4_IBF_GIRQ_POS 13
541 #define MCHP_ACPI_EC_4_OBE_GIRQ_POS 14
542 #define MCHP_ACPI_PM1_CTL_GIRQ_POS 15
543 #define MCHP_ACPI_PM1_EN_GIRQ_POS 16
544 #define MCHP_ACPI_PM1_STS_GIRQ_POS 17
545 #define MCHP_KBC_OBE_GIRQ_POS 18
546 #define MCHP_KBC_IBF_GIRQ_POS 19
547 #define MCHP_MBOX_0_GIRQ_POS 20
548 #define MCHP_P80BD_0_GIRQ_POS 22
549
550 #define MCHP_UART_0_GIRQ_BIT BIT(0)
551 #define MCHP_UART_1_GIRQ_BIT BIT(1)
552 #define MCHP_EMI_0_GIRQ_BIT BIT(2)
553 #define MCHP_EMI_1_GIRQ_BIT BIT(3)
554 #define MCHP_EMI_2_GIRQ_BIT BIT(4)
555 #define MCHP_ACPI_EC_0_IBF_GIRQ_BIT BIT(5)
556 #define MCHP_ACPI_EC_0_OBE_GIRQ_BIT BIT(6)
557 #define MCHP_ACPI_EC_1_IBF_GIRQ_BIT BIT(7)
558 #define MCHP_ACPI_EC_1_OBE_GIRQ_BIT BIT(8)
559 #define MCHP_ACPI_EC_2_IBF_GIRQ_BIT BIT(9)
560 #define MCHP_ACPI_EC_2_OBE_GIRQ_BIT BIT(10)
561 #define MCHP_ACPI_EC_3_IBF_GIRQ_BIT BIT(11)
562 #define MCHP_ACPI_EC_3_OBE_GIRQ_BIT BIT(12)
563 #define MCHP_ACPI_EC_4_IBF_GIRQ_BIT BIT(13)
564 #define MCHP_ACPI_EC_4_OBE_GIRQ_BIT BIT(14)
565 #define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
566 #define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
567 #define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
568 #define MCHP_KBC_OBE_GIRQ_BIT BIT(18)
569 #define MCHP_KBC_IBF_GIRQ_BIT BIT(19)
570 #define MCHP_MBOX_0_GIRQ_BIT BIT(20)
571 #define MCHP_P80BD_0_GIRQ_BIT BIT(22)
572 /* Masks for blocks with multiple instances or sources */
573 #define MCHP_UART_GIRQ_MASK 0x03u
574 #define MCHP_UART_EMI_GIRQ_MASK 0x1cu
575 #define MCHP_ACPI_EC_GIRQ_MASK 0x07fe0u
576 #define MCHP_ACPI_PM1_GIRQ_MASK 0x38000u
577 #define MCHP_KBC_GIRQ_MASK 0xc0000u
578 #define MCHP_HOST_PERIPH_GIRQ_MASK 0x5fffffu
579
580 #define MCHP_GIRQ15_NVIC_AGGR 7u
581 /*
582 * bitpos = MCHP_XXX_POS define
583 * Example: MCHP_GIRQ15_NVIC_DIRECT(MCHP_KBC_IBF_GIRQ_POS)
584 */
585 #define MCHP_GIRQ15_NVIC_DIRECT(bitpos) (40u + (uint32_t)(bitpos))
586
587 /* GIRQ16 Source, Enable_Set/Clr, Result registers bit positions */
588 #define MCHP_PK_GIRQ_POS 0
589 #define MCHP_RNG_GIRQ_POS 2
590 #define MCHP_AESH_GIRQ_POS 3
591
592 #define MCHP_PK_GIRQ_BIT BIT(0)
593 #define MCHP_RNG_GIRQ_BIT BIT(2)
594 #define MCHP_AESH_GIRQ_BIT BIT(3)
595 #define MCHP_CRYPTO_GIRQ_MASK 0x0du
596
597 #define MCHP_GIRQ16_NVIC_AGGR 8u
598 #define MCHP_GIRQ16_NVIC_DIRECT(bitpos) (65u + (uint32_t)(bitpos))
599
600 /* GIRQ17 Source, Enable_Set/Clr, Result registers bit positions */
601 #define MCHP_PECI_GIRQ_POS 0
602 #define MCHP_TACH_0_GIRQ_POS 1
603 #define MCHP_TACH_1_GIRQ_POS 2
604 #define MCHP_TACH_2_GIRQ_POS 3
605 #define MCHP_TACH_3_GIRQ_POS 4
606 #define MCHP_ADC_0_SGL_GIRQ_POS 8
607 #define MCHP_ADC_0_RPT_GIRQ_POS 9
608 #define MCHP_RCID_0_GIRQ_POS 10
609 #define MCHP_RCID_1_GIRQ_POS 11
610 #define MCHP_RCID_2_GIRQ_POS 12
611 #define MCHP_LED_0_GIRQ_POS 13
612 #define MCHP_LED_1_GIRQ_POS 14
613 #define MCHP_LED_2_GIRQ_POS 15
614 #define MCHP_LED_3_GIRQ_POS 16
615 #define MCHP_PHOT_0_GIRQ_POS 17
616 #define MCHP_RPMFAN_0_FAIL_GIRQ_POS 20
617 #define MCHP_RPMFAN_0_STALL_GIRQ_POS 21
618 #define MCHP_RPMFAN_1_FAIL_GIRQ_POS 22
619 #define MCHP_RPMFAN_1_STALL_GIRQ_POS 23
620
621 #define MCHP_PECI_GIRQ_BIT BIT(0)
622 #define MCHP_TACH_0_GIRQ_BIT BIT(1)
623 #define MCHP_TACH_1_GIRQ_BIT BIT(2)
624 #define MCHP_TACH_2_GIRQ_BIT BIT(3)
625 #define MCHP_TACH_3_GIRQ_BIT BIT(4)
626 #define MCHP_ADC_0_SGL_GIRQ_BIT BIT(8)
627 #define MCHP_ADC_0_RPT_GIRQ_BIT BIT(9)
628 #define MCHP_RCID_0_GIRQ_BIT BIT(10)
629 #define MCHP_RCID_1_GIRQ_BIT BIT(11)
630 #define MCHP_RCID_2_GIRQ_BIT BIT(12)
631 #define MCHP_LED_0_GIRQ_BIT BIT(13)
632 #define MCHP_LED_1_GIRQ_BIT BIT(14)
633 #define MCHP_LED_2_GIRQ_BIT BIT(15)
634 #define MCHP_LED_3_GIRQ_BIT BIT(16)
635 #define MCHP_PHOT_0_GIRQ_BIT BIT(17)
636 #define MCHP_RPMFAN_0_FAIL_GIRQ_BIT BIT(20)
637 #define MCHP_RPMFAN_0_STALL_GIRQ_BIT BIT(21)
638 #define MCHP_RPMFAN_1_FAIL_GIRQ_BIT BIT(22)
639 #define MCHP_RPMFAN_1_STALL_GIRQ_BIT BIT(23)
640 /* Masks for blocks with multiple instances or sources */
641 #define MCHP_TACH_GIRQ_MASK 0x1eu
642 #define MCHP_ADC_GIRQ_MASK 0x300u
643 #define MCHP_RCID_GIRQ_MASK 0x1c00u
644 #define MCHP_LED_GIRQ_MASK 0x1e000u
645 #define MCHP_RPMFAN_0_GIRQ_MASK 0x300000u
646 #define MCHP_RPMFAN_1_GIRQ_MASK 0xc00000u
647 #define MCHP_PERIPH_GROUP_1_MASK 0xf3ff1fu
648
649 #define MCHP_GIRQ17_NVIC_AGGR 9u
650 /* GIRQ17 direct mapping is not linear can't use parameterized macro ;<( */
651 #define MCHP_PECI_GIRQ_NVIC_DIRECT 70u
652 #define MCHP_TACH_0_GIRQ_NVIC_DIRECT 71u
653 #define MCHP_TACH_1_GIRQ_NVIC_DIRECT 72u
654 #define MCHP_TACH_2_GIRQ_NVIC_DIRECT 73u
655 #define MCHP_TACH_3_GIRQ_NVIC_DIRECT 159u
656 #define MCHP_ADC_0_SGL_GIRQ_NVIC_DIRECT 78u
657 #define MCHP_ADC_0_RPT_GIRQ_NVIC_DIRECT 79u
658 #define MCHP_RCID_0_GIRQ_NVIC_DIRECT 80u
659 #define MCHP_RCID_1_GIRQ_NVIC_DIRECT 81u
660 #define MCHP_RCID_2_GIRQ_NVIC_DIRECT 82u
661 #define MCHP_LED_0_GIRQ_NVIC_DIRECT 83u
662 #define MCHP_LED_1_GIRQ_NVIC_DIRECT 84u
663 #define MCHP_LED_2_GIRQ_NVIC_DIRECT 85u
664 #define MCHP_LED_3_GIRQ_NVIC_DIRECT 86u
665 #define MCHP_PHOT_0_GIRQ_NVIC_DIRECT 87u
666 #define MCHP_RPMFAN_0_FAIL_GIRQ_NVIC_DIRECT 74u
667 #define MCHP_RPMFAN_0_STALL_GIRQ_NVIC_DIRECT 75u
668 #define MCHP_RPMFAN_1_FAIL_GIRQ_NVIC_DIRECT 76u
669 #define MCHP_RPMFAN_1_STALL_GIRQ_NVIC_DIRECT 77u
670
671 /* GIRQ18 Source, Enable_Set/Clr, Result registers bit positions */
672 #define MCHP_SPIEP_0_GIRQ_POS 0
673 #define MCHP_QMSPI_0_GIRQ_POS 1
674 #define MCHP_GPSPI_0_TXBE_GIRQ_POS 2
675 #define MCHP_GPSPI_0_RXBF_GIRQ_POS 3
676 #define MCHP_GPSPI_1_TXBE_GIRQ_POS 4
677 #define MCHP_GPSPI_1_RXBF_GIRQ_POS 5
678 #define MCHP_BCL_0_BCLR_GIRQ_POS 6
679 #define MCHP_BCL_0_BERR_GIRQ_POS 7
680 #define MCHP_PS2_0_ACT_GIRQ_POS 10
681 #define MCHP_EERPROMC_0_GIRQ_POS 13
682 #define MCHP_CCT_0_CNT_GIRQ_POS 20
683 #define MCHP_CCT_0_CAP0_GIRQ_POS 21
684 #define MCHP_CCT_0_CAP1_GIRQ_POS 22
685 #define MCHP_CCT_0_CAP2_GIRQ_POS 23
686 #define MCHP_CCT_0_CAP3_GIRQ_POS 24
687 #define MCHP_CCT_0_CAP4_GIRQ_POS 25
688 #define MCHP_CCT_0_CAP5_GIRQ_POS 26
689 #define MCHP_CCT_0_CMP0_GIRQ_POS 27
690 #define MCHP_CCT_0_CMP1_GIRQ_POS 28
691
692 #define MCHP_SPIEP_0_GIRQ_BIT BIT(0)
693 #define MCHP_QMSPI_0_GIRQ_BIT BIT(1)
694 #define MCHP_GPSPI_0_TXBE_GIRQ_BIT BIT(2)
695 #define MCHP_GPSPI_0_RXBF_GIRQ_BIT BIT(3)
696 #define MCHP_GPSPI_1_TXBE_GIRQ_BIT BIT(4)
697 #define MCHP_GPSPI_1_RXBF_GIRQ_BIT BIT(5)
698 #define MCHP_BCL_0_BCLR_GIRQ_BIT BIT(6)
699 #define MCHP_BCL_0_BERR_GIRQ_BIT BIT(7)
700 #define MCHP_PS2_0_ACT_GIRQ_BIT BIT(10)
701 #define MCHP_EERPROMC_0_GIRQ_BIT BIT(13)
702 #define MCHP_CCT_0_CNT_GIRQ_BIT BIT(20)
703 #define MCHP_CCT_0_CAP0_GIRQ_BIT BIT(21)
704 #define MCHP_CCT_0_CAP1_GIRQ_BIT BIT(22)
705 #define MCHP_CCT_0_CAP2_GIRQ_BIT BIT(23)
706 #define MCHP_CCT_0_CAP3_GIRQ_BIT BIT(24)
707 #define MCHP_CCT_0_CAP4_GIRQ_BIT BIT(25)
708 #define MCHP_CCT_0_CAP5_GIRQ_BIT BIT(26)
709 #define MCHP_CCT_0_CMP0_GIRQ_BIT BIT(27)
710 #define MCHP_CCT_0_CMP1_GIRQ_BIT BIT(28)
711 /* Masks for blocks with multiple instances or sources */
712 #define MCHP_GPSPI_0_GIRQ_MASK 0x0cu
713 #define MCHP_GPSPI_1_GIRQ_MASK 0x30u
714 #define MCHP_BCL_0_GIRQ_MASK 0xc0u
715 #define MCHP_CCT_0_GIRQ_MASK 0x1ff00000u
716 #define MCHP_PERIPH_GROUP_2_MASK 0x1ff024ffu
717
718 #define MCHP_GIRQ18_NVIC_AGGR 10u
719 /* GIRQ18 direct mapping is not linear can't use parameterized macro ;<( */
720 #define MCHP_SPIEP_0_GIRQ_NVIC_DIRECT 90u
721 #define MCHP_QMSPI_0_GIRQ_NVIC_DIRECT 91u
722 #define MCHP_GPSPI_0_TXBE_GIRQ_NVIC_DIRECT 92u
723 #define MCHP_GPSPI_0_RXBF_GIRQ_NVIC_DIRECT 93u
724 #define MCHP_GPSPI_1_TXBE_GIRQ_NVIC_DIRECT 94u
725 #define MCHP_GPSPI_1_RXBF_GIRQ_NVIC_DIRECT 95u
726 #define MCHP_BCL_0_BCLR_GIRQ_NVIC_DIRECT 97u
727 #define MCHP_BCL_0_BERR_GIRQ_NVIC_DIRECT 96u
728 #define MCHP_PS2_0_ACT_GIRQ_NVIC_DIRECT 100u
729 #define MCHP_EERPROMC_0_GIRQ_NVIC_DIRECT 155u
730 #define MCHP_CCT_0_CNT_GIRQ_NVIC_DIRECT 146u
731 #define MCHP_CCT_0_CAP0_GIRQ_NVIC_DIRECT 147u
732 #define MCHP_CCT_0_CAP1_GIRQ_NVIC_DIRECT 148u
733 #define MCHP_CCT_0_CAP2_GIRQ_NVIC_DIRECT 149u
734 #define MCHP_CCT_0_CAP3_GIRQ_NVIC_DIRECT 150u
735 #define MCHP_CCT_0_CAP4_GIRQ_NVIC_DIRECT 151u
736 #define MCHP_CCT_0_CAP5_GIRQ_NVIC_DIRECT 152u
737 #define MCHP_CCT_0_CMP0_GIRQ_NVIC_DIRECT 153u
738 #define MCHP_CCT_0_CMP1_GIRQ_NVIC_DIRECT 154u
739
740 /* GIRQ19 Source, Enable_Set/Clr, Result registers bit positions */
741 #define MCHP_ESPI_PC_GIRQ_POS 0
742 #define MCHP_ESPI_BM1_GIRQ_POS 1
743 #define MCHP_ESPI_BM2_GIRQ_POS 2
744 #define MCHP_ESPI_LTR_GIRQ_POS 3
745 #define MCHP_ESPI_OOB_UP_GIRQ_POS 4
746 #define MCHP_ESPI_OOB_DN_GIRQ_POS 5
747 #define MCHP_ESPI_FC_GIRQ_POS 6
748 #define MCHP_ESPI_RESET_GIRQ_POS 7
749 #define MCHP_ESPI_VW_EN_GIRQ_POS 8
750 #define MCHP_ESPI_SAF_DONE_GIRQ_POS 9
751 #define MCHP_ESPI_SAF_ERR_GIRQ_POS 10
752 #define MCHP_ESPI_SAF_CACHE_GIRQ_POS 11
753
754 #define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
755 #define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
756 #define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
757 #define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
758 #define MCHP_ESPI_OOB_UP_GIRQ_BIT BIT(4)
759 #define MCHP_ESPI_OOB_DN_GIRQ_BIT BIT(5)
760 #define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
761 #define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
762 #define MCHP_ESPI_VWEN_GIRQ_BIT BIT(8)
763 #define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
764 #define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
765 #define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11)
766 /* Masks for blocks with multiple instances or sources */
767 #define MCHP_ESPI_BM_GIRQ_MASK 0x006u
768 #define MCHP_ESPI_OOB_GIRQ_MASK 0x030u
769 #define MCHP_ESPI_SAF_GIRQ_MASK 0xe00u
770 #define MCHP_ESPI_GIRQ_MASK 0xfffu
771
772 #define MCHP_GIRQ19_NVIC_AGGR 11u
773 #define MCHP_ESPI_PC_GIRQ_NVIC_DIRECT 103u
774 #define MCHP_ESPI_BM1_GIRQ_NVIC_DIRECT 104u
775 #define MCHP_ESPI_BM2_GIRQ_NVIC_DIRECT 105u
776 #define MCHP_ESPI_LTR_GIRQ_NVIC_DIRECT 106u
777 #define MCHP_ESPI_OOB_UP_GIRQ_NVIC_DIRECT 107u
778 #define MCHP_ESPI_OOB_DN_GIRQ_NVIC_DIRECT 108u
779 #define MCHP_ESPI_FC_GIRQ_NVIC_DIRECT 109u
780 #define MCHP_ESPI_RESET_GIRQ_NVIC_DIRECT 110u
781 #define MCHP_ESPI_VWEN_GIRQ_NVIC_DIRECT 156u
782 #define MCHP_ESPI_SAF_DONE_GIRQ_NVIC_DIRECT 166u
783 #define MCHP_ESPI_SAF_ERR_GIRQ_NVIC_DIRECT 167u
784 #define MCHP_ESPI_SAF_CACHE_GIRQ_NVIC_DIRECT 169u
785
786 /* GIRQ20 Source, Enable_Set/Clr, Result registers bit positions */
787 #define MCHP_STAP_OBF_GIRQ_POS 0
788 #define MCHP_STAP_IBF_GIRQ_POS 1
789 #define MCHP_STAP_WAKE_GIRQ_POS 2
790 #define MCHP_OTP_READY_GIRQ_POS 3
791 #define MCHP_ISPI_ERR_GIRQ_POS 8
792 #define MCHP_CLK32_MON_GIRQ_POS 9
793
794 #define MCHP_STAP_OBF_GIRQ_BIT BIT(0)
795 #define MCHP_STAP_IBF_GIRQ_BIT BIT(1)
796 #define MCHP_STAP_WAKE_GIRQ_BIT BIT(2)
797 #define MCHP_OTP_READY_GIRQ_BIT BIT(3)
798 #define MCHP_ISPI_ERR_GIRQ_BIT BIT(8)
799 #define MCHP_CLK32_MON_GIRQ_BIT BIT(9)
800 /* Masks for blocks with multiple instances or sources */
801 #define MCHP_STAP_GIRQ_MASK 0x007u
802 #define MCHP_PERIPH_GROUP_3_MASK 0x30fu
803
804 #define MCHP_GIRQ20_NVIC_AGGR 12u
805 /*
806 * Warning: STAP has no direct connections. If STAP and other source are
807 * enabled GIRQ20 must be used in aggregated mode.
808 */
809 #define MCHP_OTP_READY_GIRQ_NVIC_DIRECT 173u
810 #define MCHP_CLK32_MON_GIRQ_NVIC_DIRECT 174u
811
812 /* GIRQ21 Source, Enable_Set/Clr, Result registers bit positions */
813 #define MCHP_WDT_GIRQ_POS 2
814 #define MCHP_WTMR_ALARM_GIRQ_POS 3
815 #define MCHP_WTMR_SUBWK_GIRQ_POS 4
816 #define MCHP_WTMR_ONESEC_GIRQ_POS 5
817 #define MCHP_WTMR_SUBSEC_GIRQ_POS 6
818 #define MCHP_WTMR_SPP_GIRQ_POS 7
819 #define MCHP_RTC_GIRQ_POS 8
820 #define MCHP_RTC_ALARM_GIRQ_POS 9
821 #define MCHP_VCI_OVRD_IN_GIRQ_POS 10
822 #define MCHP_VCI_IN0_GIRQ_POS 11
823 #define MCHP_VCI_IN1_GIRQ_POS 12
824 #define MCHP_VCI_IN2_GIRQ_POS 13
825 #define MCHP_VCI_IN3_GIRQ_POS 14
826 #define MCHP_VCI_IN4_GIRQ_POS 15
827 #define MCHP_PS2_0_PORT0A_WK_GIRQ_POS 18
828 #define MCHP_PS2_0_PORT0B_WK_GIRQ_POS 19
829 #define MCHP_KEYSCAN_GIRQ_POS 25
830 #define MCHP_GLUE_GIRQ_POS 26
831
832 #define MCHP_WDT_GIRQ_BIT BIT(2)
833 #define MCHP_WTMR_ALARM_GIRQ_BIT BIT(3)
834 #define MCHP_WTMR_SUBWK_GIRQ_BIT BIT(4)
835 #define MCHP_WTMR_ONESEC_GIRQ_BIT BIT(5)
836 #define MCHP_WTMR_SUBSEC_GIRQ_BIT BIT(6)
837 #define MCHP_WTMR_SPP_GIRQ_BIT BIT(7)
838 #define MCHP_RTC_GIRQ_BIT BIT(8)
839 #define MCHP_RTC_ALARM_GIRQ_BIT BIT(9)
840 #define MCHP_VCI_OVRD_IN_GIRQ_BIT BIT(10)
841 #define MCHP_VCI_IN0_GIRQ_BIT BIT(11)
842 #define MCHP_VCI_IN1_GIRQ_BIT BIT(12)
843 #define MCHP_VCI_IN2_GIRQ_BIT BIT(13)
844 #define MCHP_VCI_IN3_GIRQ_BIT BIT(14)
845 #define MCHP_VCI_IN4_GIRQ_BIT BIT(15)
846 #define MCHP_PS2_0_PORT0A_WK_GIRQ_BIT BIT(18)
847 #define MCHP_PS2_0_PORT0B_WK_GIRQ_BIT BIT(19)
848 #define MCHP_KEYSCAN_GIRQ_BIT BIT(25)
849 #define MCHP_GLUE_GIRQ_BIT BIT(26)
850 /* Masks for blocks with multiple instances or sources */
851 #define MCHP_WTMR_GIRQ_MASK 0xf8u
852 #define MCHP_RTC_GIRQ_MASK 0x300u
853 #define MCHP_VCI_GIRQ_MASK 0xfc00u
854 #define MCHP_PS2_PORT_WK_GIRQ_MASK 0xc0000u
855 #define MCHP_PERIPH_GROUP_4_MASK 0x60cfffcu
856
857 #define MCHP_GIRQ21_NVIC_AGGR 13u
858 #define MCHP_WDT_GIRQ_NVIC_DIRECT 171u
859 #define MCHP_WTMR_ALARM_GIRQ_NVIC_DIRECT 114u
860 #define MCHP_WTMR_SUBWK_GIRQ_NVIC_DIRECT 115u
861 #define MCHP_WTMR_ONESEC_GIRQ_NVIC_DIRECT 116u
862 #define MCHP_WTMR_SUBSEC_GIRQ_NVIC_DIRECT 117u
863 #define MCHP_WTMR_SPP_GIRQ_NVIC_DIRECT 118u
864 #define MCHP_RTC_GIRQ_NVIC_DIRECT 119u
865 #define MCHP_RTC_ALARM_GIRQ_NVIC_DIRECT 120u
866 #define MCHP_VCI_OVRD_IN_GIRQ_NVIC_DIRECT 121u
867 #define MCHP_VCI_IN0_GIRQ_NVIC_DIRECT 122u
868 #define MCHP_VCI_IN1_GIRQ_NVIC_DIRECT 123u
869 #define MCHP_VCI_IN2_GIRQ_NVIC_DIRECT 124u
870 #define MCHP_VCI_IN3_GIRQ_NVIC_DIRECT 125u
871 #define MCHP_VCI_IN4_GIRQ_NVIC_DIRECT 126u
872 #define MCHP_PS2_0_PORT0A_WK_GIRQ_NVIC_DIRECT 129u
873 #define MCHP_PS2_0_PORT0B_WK_GIRQ_NVIC_DIRECT 130u
874 #define MCHP_KEYSCAN_GIRQ_NVIC_DIRECT 135u
875 #define MCHP_GLUE_GIRQ_NVIC_DIRECT 172u
876
877 /*
878 * GIRQ22 Source, Enable_Set/Clr, Result registers bit positions
879 * NOTE: These wake sources allow the peripheral to turn back on clocks
880 * long enough to facilite the data transfer. No interrupt to the EC occurs
881 * unless the peripheral was configured to generate an EC interrupt for
882 * the specific data transfer.
883 */
884 #define MCHP_SPIEP_WK_CLK_GIRQ_POS 0
885 #define MCHP_I2C_SMB_0_WK_CLK_GIRQ_POS 1
886 #define MCHP_I2C_SMB_1_WK_CLK_GIRQ_POS 2
887 #define MCHP_I2C_SMB_2_WK_CLK_GIRQ_POS 3
888 #define MCHP_I2C_SMB_3_WK_CLK_GIRQ_POS 4
889 #define MCHP_I2C_SMB_4_WK_CLK_GIRQ_POS 5
890 #define MCHP_ESPI_WK_CLK_GIRQ_POS 9
891 #define MCHP_STAP_WK_CLK_GIRQ_POS 15
892
893 #define MCHP_SPIEP_WK_CLK_GIRQ_BIT BIT(0)
894 #define MCHP_I2C_SMB_0_WK_CLK_GIRQ_BIT BIT(1)
895 #define MCHP_I2C_SMB_1_WK_CLK_GIRQ_BIT BIT(2)
896 #define MCHP_I2C_SMB_2_WK_CLK_GIRQ_BIT BIT(3)
897 #define MCHP_I2C_SMB_3_WK_CLK_GIRQ_BIT BIT(4)
898 #define MCHP_I2C_SMB_4_WK_CLK_GIRQ_BIT BIT(5)
899 #define MCHP_ESPI_WK_CLK_GIRQ_BIT BIT(9)
900 #define MCHP_STAP_WK_CLK_GIRQ_BIT BIT(15)
901 /* Masks for blocks with multiple instances or sources */
902 #define MCHP_I2C_SMB_WK_CLK_GIRQ_MASK 0x3eu
903 #define MCHP_CLK_WK_CLK_GIRQ_MASK 0x823fu
904
905 /* GIRQ23 Source, Enable_Set/Clr, Result registers bit positions */
906 #define MCHP_BTMR16_0_GIRQ_POS 0
907 #define MCHP_BTMR16_1_GIRQ_POS 1
908 #define MCHP_BTMR16_2_GIRQ_POS 2
909 #define MCHP_BTMR16_3_GIRQ_POS 3
910 #define MCHP_BTMR32_0_GIRQ_POS 4
911 #define MCHP_BTMR32_1_GIRQ_POS 5
912 #define MCHP_CTMR_0_GIRQ_POS 6
913 #define MCHP_CTMR_1_GIRQ_POS 7
914 #define MCHP_CTMR_2_GIRQ_POS 8
915 #define MCHP_CTMR_3_GIRQ_POS 9
916 #define MCHP_RTMR_0_GIRQ_POS 10
917 #define MCHP_RTMR_0_SWI0_GIRQ_POS 11
918 #define MCHP_RTMR_0_SWI1_GIRQ_POS 12
919 #define MCHP_RTMR_0_SWI2_GIRQ_POS 13
920 #define MCHP_RTMR_0_SWI3_GIRQ_POS 14
921 #define MCHP_HTMR_0_GIRQ_POS 16
922 #define MCHP_HTMR_1_GIRQ_POS 17
923
924 #define MCHP_BTMR16_0_GIRQ_BIT BIT(0)
925 #define MCHP_BTMR16_1_GIRQ_BIT BIT(1)
926 #define MCHP_BTMR16_2_GIRQ_BIT BIT(2)
927 #define MCHP_BTMR16_3_GIRQ_BIT BIT(3)
928 #define MCHP_BTMR32_0_GIRQ_BIT BIT(4)
929 #define MCHP_BTMR32_1_GIRQ_BIT BIT(5)
930 #define MCHP_CTMR_0_GIRQ_BIT BIT(6)
931 #define MCHP_CTMR_1_GIRQ_BIT BIT(7)
932 #define MCHP_CTMR_2_GIRQ_BIT BIT(8)
933 #define MCHP_CTMR_3_GIRQ_BIT BIT(9)
934 #define MCHP_RTMR_0_GIRQ_BIT BIT(10)
935 #define MCHP_RTMR_0_SWI0_GIRQ_BIT BIT(11)
936 #define MCHP_RTMR_0_SWI1_GIRQ_BIT BIT(12)
937 #define MCHP_RTMR_0_SWI2_GIRQ_BIT BIT(13)
938 #define MCHP_RTMR_0_SWI3_GIRQ_BIT BIT(14)
939 #define MCHP_HTMR_0_GIRQ_BIT BIT(16)
940 #define MCHP_HTMR_1_GIRQ_BIT BIT(17)
941 /* Masks for blocks with multiple instances or sources */
942 #define MCHP_BTMR16_GIRQ_MASK 0x0fu
943 #define MCHP_BTMR32_GIRQ_MASK 0x30u
944 #define MCHP_CTMR_GIRQ_MASK 0x3c0u
945 #define MCHP_RMTR_GIRQ_MASK 0x7c00u
946 #define MCHP_HTMR_GIRQ_MASK 0x30000u
947 #define MCHP_PERIPH_GROUP_5_GIRQ_MASK 0x37fffu
948
949 #define MCHP_GIRQ23_NVIC_AGGR 14u
950 /*
951 * Warning: RTMR SWI interrupts have no direct connection.
952 * If RTMR SWI will be used GIRQ23 must be aggregated.
953 */
954 #define MCHP_BTMR16_0_GIRQ_NVIC_DIRECT 136u
955 #define MCHP_BTMR16_1_GIRQ_NVIC_DIRECT 137u
956 #define MCHP_BTMR16_2_GIRQ_NVIC_DIRECT 138u
957 #define MCHP_BTMR16_3_GIRQ_NVIC_DIRECT 139u
958 #define MCHP_BTMR32_0_GIRQ_NVIC_DIRECT 140u
959 #define MCHP_BTMR32_1_GIRQ_NVIC_DIRECT 141u
960 #define MCHP_CTMR_0_GIRQ_NVIC_DIRECT 142u
961 #define MCHP_CTMR_1_GIRQ_NVIC_DIRECT 143u
962 #define MCHP_CTMR_2_GIRQ_NVIC_DIRECT 144u
963 #define MCHP_CTMR_3_GIRQ_NVIC_DIRECT 145u
964 #define MCHP_RTMR_0_GIRQ_NVIC_DIRECT 111u
965 #define MCHP_HTMR_0_GIRQ_NVIC_DIRECT 112u
966 #define MCHP_HTMR_1_GIRQ_NVIC_DIRECT 113u
967
968 /* GIRQ24 Source, Enable_Set/Clr, Result registers bit positions */
969 #define MCHP_MSVW00_SRC0_GIRQ_POS 0
970 #define MCHP_MSVW00_SRC1_GIRQ_POS 1
971 #define MCHP_MSVW00_SRC2_GIRQ_POS 2
972 #define MCHP_MSVW00_SRC3_GIRQ_POS 3
973 #define MCHP_MSVW01_SRC0_GIRQ_POS 4
974 #define MCHP_MSVW01_SRC1_GIRQ_POS 5
975 #define MCHP_MSVW01_SRC2_GIRQ_POS 6
976 #define MCHP_MSVW01_SRC3_GIRQ_POS 7
977 #define MCHP_MSVW02_SRC0_GIRQ_POS 8
978 #define MCHP_MSVW02_SRC1_GIRQ_POS 9
979 #define MCHP_MSVW02_SRC2_GIRQ_POS 10
980 #define MCHP_MSVW02_SRC3_GIRQ_POS 11
981 #define MCHP_MSVW03_SRC0_GIRQ_POS 12
982 #define MCHP_MSVW03_SRC1_GIRQ_POS 13
983 #define MCHP_MSVW03_SRC2_GIRQ_POS 14
984 #define MCHP_MSVW03_SRC3_GIRQ_POS 15
985 #define MCHP_MSVW04_SRC0_GIRQ_POS 16
986 #define MCHP_MSVW04_SRC1_GIRQ_POS 17
987 #define MCHP_MSVW04_SRC2_GIRQ_POS 18
988 #define MCHP_MSVW04_SRC3_GIRQ_POS 19
989 #define MCHP_MSVW05_SRC0_GIRQ_POS 20
990 #define MCHP_MSVW05_SRC1_GIRQ_POS 21
991 #define MCHP_MSVW05_SRC2_GIRQ_POS 22
992 #define MCHP_MSVW05_SRC3_GIRQ_POS 23
993 #define MCHP_MSVW06_SRC0_GIRQ_POS 24
994 #define MCHP_MSVW06_SRC1_GIRQ_POS 25
995 #define MCHP_MSVW06_SRC2_GIRQ_POS 26
996 #define MCHP_MSVW06_SRC3_GIRQ_POS 27
997
998 #define MCHP_MSVW00_SRC0_GIRQ_BIT BIT(0)
999 #define MCHP_MSVW00_SRC1_GIRQ_BIT BIT(1)
1000 #define MCHP_MSVW00_SRC2_GIRQ_BIT BIT(2)
1001 #define MCHP_MSVW00_SRC3_GIRQ_BIT BIT(3)
1002 #define MCHP_MSVW01_SRC0_GIRQ_BIT BIT(4)
1003 #define MCHP_MSVW01_SRC1_GIRQ_BIT BIT(5)
1004 #define MCHP_MSVW01_SRC2_GIRQ_BIT BIT(6)
1005 #define MCHP_MSVW01_SRC3_GIRQ_BIT BIT(7)
1006 #define MCHP_MSVW02_SRC0_GIRQ_BIT BIT(8)
1007 #define MCHP_MSVW02_SRC1_GIRQ_BIT BIT(9)
1008 #define MCHP_MSVW02_SRC2_GIRQ_BIT BIT(10)
1009 #define MCHP_MSVW02_SRC3_GIRQ_BIT BIT(11)
1010 #define MCHP_MSVW03_SRC0_GIRQ_BIT BIT(12)
1011 #define MCHP_MSVW03_SRC1_GIRQ_BIT BIT(13)
1012 #define MCHP_MSVW03_SRC2_GIRQ_BIT BIT(14)
1013 #define MCHP_MSVW03_SRC3_GIRQ_BIT BIT(15)
1014 #define MCHP_MSVW04_SRC0_GIRQ_BIT BIT(16)
1015 #define MCHP_MSVW04_SRC1_GIRQ_BIT BIT(17)
1016 #define MCHP_MSVW04_SRC2_GIRQ_BIT BIT(18)
1017 #define MCHP_MSVW04_SRC3_GIRQ_BIT BIT(19)
1018 #define MCHP_MSVW05_SRC0_GIRQ_BIT BIT(20)
1019 #define MCHP_MSVW05_SRC1_GIRQ_BIT BIT(21)
1020 #define MCHP_MSVW05_SRC2_GIRQ_BIT BIT(22)
1021 #define MCHP_MSVW05_SRC3_GIRQ_BIT BIT(23)
1022 #define MCHP_MSVW06_SRC0_GIRQ_BIT BIT(24)
1023 #define MCHP_MSVW06_SRC1_GIRQ_BIT BIT(25)
1024 #define MCHP_MSVW06_SRC2_GIRQ_BIT BIT(26)
1025 #define MCHP_MSVW06_SRC3_GIRQ_BIT BIT(27)
1026 /* Masks for blocks with multiple instances or sources */
1027 #define MCHP_MSVW00_GIRQ_MASK 0xfu
1028 #define MCHP_MSVW01_GIRQ_MASK 0xf0u
1029 #define MCHP_MSVW02_GIRQ_MASK 0xf00u
1030 #define MCHP_MSVW03_GIRQ_MASK 0xf000u
1031 #define MCHP_MSVW04_GIRQ_MASK 0xf0000u
1032 #define MCHP_MSVW05_GIRQ_MASK 0xf00000u
1033 #define MCHP_MSVW06_GIRQ_MASK 0xf000000u
1034 #define MCHP_MSVW00_06_GIRQ_MASK 0x0fffffffu
1035
1036 #define MCHP_GIRQ24_NVIC_AGGR 15u
1037
1038 /* GIRQ25 Source, Enable_Set/Clr, Result registers bit positions */
1039 #define MCHP_MSVW07_SRC0_GIRQ_POS 0
1040 #define MCHP_MSVW07_SRC1_GIRQ_POS 1
1041 #define MCHP_MSVW07_SRC2_GIRQ_POS 2
1042 #define MCHP_MSVW07_SRC3_GIRQ_POS 3
1043 #define MCHP_MSVW08_SRC0_GIRQ_POS 4
1044 #define MCHP_MSVW08_SRC1_GIRQ_POS 5
1045 #define MCHP_MSVW08_SRC2_GIRQ_POS 6
1046 #define MCHP_MSVW08_SRC3_GIRQ_POS 7
1047 #define MCHP_MSVW09_SRC0_GIRQ_POS 8
1048 #define MCHP_MSVW09_SRC1_GIRQ_POS 9
1049 #define MCHP_MSVW09_SRC2_GIRQ_POS 10
1050 #define MCHP_MSVW09_SRC3_GIRQ_POS 11
1051 #define MCHP_MSVW10_SRC0_GIRQ_POS 12
1052 #define MCHP_MSVW10_SRC1_GIRQ_POS 13
1053 #define MCHP_MSVW10_SRC2_GIRQ_POS 14
1054 #define MCHP_MSVW10_SRC3_GIRQ_POS 15
1055
1056 #define MCHP_MSVW07_SRC0_GIRQ_BIT BIT(0)
1057 #define MCHP_MSVW07_SRC1_GIRQ_BIT BIT(1)
1058 #define MCHP_MSVW07_SRC2_GIRQ_BIT BIT(2)
1059 #define MCHP_MSVW07_SRC3_GIRQ_BIT BIT(3)
1060 #define MCHP_MSVW08_SRC0_GIRQ_BIT BIT(4)
1061 #define MCHP_MSVW08_SRC1_GIRQ_BIT BIT(5)
1062 #define MCHP_MSVW08_SRC2_GIRQ_BIT BIT(6)
1063 #define MCHP_MSVW08_SRC3_GIRQ_BIT BIT(7)
1064 #define MCHP_MSVW09_SRC0_GIRQ_BIT BIT(8)
1065 #define MCHP_MSVW09_SRC1_GIRQ_BIT BIT(9)
1066 #define MCHP_MSVW09_SRC2_GIRQ_BIT BIT(10)
1067 #define MCHP_MSVW09_SRC3_GIRQ_BIT BIT(11)
1068 #define MCHP_MSVW10_SRC0_GIRQ_BIT BIT(12)
1069 #define MCHP_MSVW10_SRC1_GIRQ_BIT BIT(13)
1070 #define MCHP_MSVW10_SRC2_GIRQ_BIT BIT(14)
1071 #define MCHP_MSVW10_SRC3_GIRQ_BIT BIT(15)
1072 /* Masks for blocks with multiple instances or sources */
1073 #define MCHP_MSVW07_GIRQ_MASK 0xfu
1074 #define MCHP_MSVW08_GIRQ_MASK 0xf0u
1075 #define MCHP_MSVW09_GIRQ_MASK 0xf00u
1076 #define MCHP_MSVW10_GIRQ_MASK 0xf000u
1077 #define MCHP_MSVW07_10_GIRQ_MASK 0xffffu
1078
1079 #define MCHP_GIRQ25_NVIC_AGGR 16u
1080
1081 /* GIRQ26 Source, Enable_Set/Clr, Result registers bit positions */
1082 #define MCHP_GPIO_0240_GIRQ_POS 0
1083 #define MCHP_GPIO_0241_GIRQ_POS 1
1084 #define MCHP_GPIO_0242_GIRQ_POS 2
1085 #define MCHP_GPIO_0243_GIRQ_POS 3
1086 #define MCHP_GPIO_0244_GIRQ_POS 4
1087 #define MCHP_GPIO_0245_GIRQ_POS 5
1088 #define MCHP_GPIO_0246_GIRQ_POS 6
1089 #define MCHP_GPIO_0254_GIRQ_POS 12
1090 #define MCHP_GPIO_0255_GIRQ_POS 13
1091
1092 #define MCHP_GPIO_0240_GIRQ_BIT BIT(0)
1093 #define MCHP_GPIO_0241_GIRQ_BIT BIT(1)
1094 #define MCHP_GPIO_0242_GIRQ_BIT BIT(2)
1095 #define MCHP_GPIO_0243_GIRQ_BIT BIT(3)
1096 #define MCHP_GPIO_0244_GIRQ_BIT BIT(4)
1097 #define MCHP_GPIO_0245_GIRQ_BIT BIT(5)
1098 #define MCHP_GPIO_0246_GIRQ_BIT BIT(6)
1099 #define MCHP_GPIO_0254_GIRQ_BIT BIT(12)
1100 #define MCHP_GPIO_0255_GIRQ_BIT BIT(13)
1101 /* Masks for blocks with multiple instances or sources */
1102 #define MCHP_GPIO_0240_0276_GIRQ_MASK 0x307fu
1103
1104 #define MCHP_GIRQ26_NVIC_AGGR 17u
1105
1106 /* GIRQ numbering */
1107 #define MCHP_GIRQ_START_NUM 8u
1108 #define MCHP_GIRQ_LAST_NUM 26u
1109 #define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8u)
1110 #define MCHP_GIRQ_IDX_FIRST 0u
1111 #define MCHP_GIRQ_IDX_MAX 19u
1112 /* Number of NVIC Enable_Set/Clr, Pending_Set/Clr, Active 32-bit registers */
1113 #define MCHP_MAX_NVIC_IDX 6u
1114 /* Number of external NVIC inputs */
1115 #define MCHP_MAX_NVIC_EXT_INPUTS 181u
1116
1117 /** @brief GIRQ registers. Total size = 20(0x14) bytes */
1118 struct girq_regs {
1119 volatile uint32_t SRC;
1120 volatile uint32_t EN_SET;
1121 volatile uint32_t RESULT;
1122 volatile uint32_t EN_CLR;
1123 uint32_t RSVD1[1];
1124 };
1125
1126 /** @brief ECIA registers with each GIRQ elucidated */
1127 struct ecia_named_regs {
1128 struct girq_regs GIRQ08;
1129 struct girq_regs GIRQ09;
1130 struct girq_regs GIRQ10;
1131 struct girq_regs GIRQ11;
1132 struct girq_regs GIRQ12;
1133 struct girq_regs GIRQ13;
1134 struct girq_regs GIRQ14;
1135 struct girq_regs GIRQ15;
1136 struct girq_regs GIRQ16;
1137 struct girq_regs GIRQ17;
1138 struct girq_regs GIRQ18;
1139 struct girq_regs GIRQ19;
1140 struct girq_regs GIRQ20;
1141 struct girq_regs GIRQ21;
1142 struct girq_regs GIRQ22;
1143 struct girq_regs GIRQ23;
1144 struct girq_regs GIRQ24;
1145 struct girq_regs GIRQ25;
1146 struct girq_regs GIRQ26;
1147 uint8_t RSVD2[(0x0200 - 0x017c)];
1148 volatile uint32_t BLK_EN_SET;
1149 volatile uint32_t BLK_EN_CLR;
1150 volatile uint32_t BLK_ACTIVE;
1151 };
1152
1153 /** @brief ECIA registers with array of GIRQ's */
1154 struct ecia_regs {
1155 struct girq_regs GIRQ[19];
1156 uint8_t RSVD2[(0x200 - 0x17c)];
1157 volatile uint32_t BLK_EN_SET;
1158 volatile uint32_t BLK_EN_CLR;
1159 volatile uint32_t BLK_ACTIVE;
1160 };
1161
1162 /* Until XEC ECIA driver is available we define these locally */
mchp_soc_ecia_girq_aggr_en(uint8_t girq,uint8_t en)1163 static inline void mchp_soc_ecia_girq_aggr_en(uint8_t girq, uint8_t en)
1164 {
1165 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {
1166 return;
1167 }
1168
1169 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1170
1171 if (en) {
1172 ecia->BLK_EN_SET = BIT(girq);
1173 } else {
1174 ecia->BLK_EN_CLR = BIT(girq);
1175 }
1176 }
1177
mchp_soc_ecia_girq_src_clr(uint8_t girq,uint8_t pin)1178 static inline void mchp_soc_ecia_girq_src_clr(uint8_t girq, uint8_t pin)
1179 {
1180 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||
1181 (pin > 31)) {
1182 return;
1183 }
1184
1185 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1186
1187 ecia->GIRQ[girq - 8u].SRC = BIT(pin);
1188 }
1189
mchp_soc_ecia_girq_src_clr_bitmap(uint8_t girq,uint32_t bitmap)1190 static inline void mchp_soc_ecia_girq_src_clr_bitmap(uint8_t girq,
1191 uint32_t bitmap)
1192 {
1193 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {
1194 return;
1195 }
1196
1197 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1198
1199 ecia->GIRQ[girq - 8u].SRC = bitmap;
1200 }
1201
mchp_soc_ecia_girq_src_dis(uint8_t girq,uint8_t pin)1202 static inline void mchp_soc_ecia_girq_src_dis(uint8_t girq, uint8_t pin)
1203 {
1204 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||
1205 (pin > 31)) {
1206 return;
1207 }
1208
1209 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1210
1211 ecia->GIRQ[girq - 8u].EN_CLR = BIT(pin);
1212 }
1213
mchp_soc_ecia_girq_src_en(uint8_t girq,uint8_t pin)1214 static inline void mchp_soc_ecia_girq_src_en(uint8_t girq, uint8_t pin)
1215 {
1216 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS) ||
1217 (pin > 31)) {
1218 return;
1219 }
1220
1221 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1222
1223 ecia->GIRQ[girq - 8u].EN_SET = BIT(pin);
1224 }
1225
mchp_soc_ecia_girq_result(uint8_t girq)1226 static inline uint32_t mchp_soc_ecia_girq_result(uint8_t girq)
1227 {
1228 if ((girq < MCHP_FIRST_GIRQ_NOS) || (girq > MCHP_LAST_GIRQ_NOS)) {
1229 return 0u;
1230 }
1231
1232 struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
1233
1234 return ecia->GIRQ[girq - 8u].RESULT;
1235 }
1236
1237 #endif /* #ifndef _MEC172X_ECIA_H */
1238