1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_ESPI_SAF_H_ 8 #define _MEC172X_ESPI_SAF_H_ 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u 14 #define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u 15 16 /* SAF hardware supports up to 2 external SPI flash devices */ 17 #define MCHP_ESPI_SAF_CS_MAX 2 18 19 /* Three TAG Map registers */ 20 #define MCHP_ESPI_SAF_TAGMAP_MAX 3 21 /* 17 protection regions */ 22 #define MCHP_ESPI_SAF_PR_MAX 17 23 24 #define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0u 25 #define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2u 26 27 #define MCHP_ESPI_SAF_BASE 0x40008000u 28 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000u 29 #define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8u 30 #define MCHP_ESPI_SAF_COMM_MODE_ADDR (MCHP_ESPI_SAF_COMM_BASE_ADDR + \ 31 MCHP_ESPI_SAF_COMM_MODE_OFS) 32 33 /* SAF Protection region described by 4 32-bit registers. 17 regions */ 34 #define MCHP_ESPI_SAF_PROT_MAX 17u 35 36 /* Register bit definitions */ 37 38 /* SAF EC Portal Command register */ 39 #define MCHP_SAF_ECP_CMD_OFS 0x18u 40 #define MCHP_SAF_ECP_CMD_MASK 0xff00ffffu 41 #define MCHP_SAF_ECP_CMD_PUT_POS 0 42 #define MCHP_SAF_ECP_CMD_PUT_MASK 0xffu 43 #define MCHP_SAF_ECP_CMD_PUT_FLASH_NP 0x0au 44 #define MCHP_SAF_ECP_CMD_CTYPE_POS 8 45 #define MCHP_SAF_ECP_CMD_CTYPE_READ0 0x00u 46 #define MCHP_SAF_ECP_CMD_CTYPE_WRITE0 0x01u 47 #define MCHP_SAF_ECP_CMD_CTYPE_ERASE0 0x02u 48 #define MCHP_SAF_ECP_CMD_CTYPE_MAX0 0x03u 49 #define MCHP_SAF_ECP_CMD_CTYPE_MASK 0xff00ul 50 #define MCHP_SAF_ECP_CMD_CTYPE_READ 0x0000ul 51 #define MCHP_SAF_ECP_CMD_CTYPE_WRITE 0x0100ul 52 #define MCHP_SAF_ECP_CMD_CTYPE_ERASE 0x0200ul 53 #define MCHP_SAF_ECP_CMD_LEN_POS 24 54 #define MCHP_SAF_ECP_CMD_LEN_MASK0 0xffu 55 #define MCHP_SAF_ECP_CMD_LEN_MASK 0xff000000ul 56 /* Read/Write request size (1 <= reqlen <= 64) bytes */ 57 #define MCHP_SAF_ECP_CMD_RW_LEN_MIN 1u 58 #define MCHP_SAF_ECP_CMD_RW_LEN_MAX 64u 59 /* Only three erase sizes are supported encoded as */ 60 #define MCHP_SAF_ECP_CMD_ERASE_4K 0u 61 #define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24) 62 #define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25) 63 64 /* SAF EC Portal Flash Address register */ 65 #define MCHP_SAF_ECP_FLAR_OFS 0x1cu 66 #define MCHP_SAF_ECP_FLAR_MASK 0xffffffffu 67 68 /* SAF EC Portal Start register */ 69 #define MCHP_SAF_ECP_START_OFS 0x20u 70 #define MCHP_SAF_ECP_START_MASK 0x01u 71 #define MCHP_SAF_ECP_START BIT(0) 72 73 /* SAF EC Portal Buffer Address register */ 74 #define MCHP_SAF_ECP_BFAR_OFS 0x24u 75 #define MCHP_SAF_ECP_BFAR_MASK 0xfffffffcu 76 77 /* SAF EC Portal Status register */ 78 #define MCHP_SAF_ECP_STS_OFS 0x28u 79 #define MCHP_SAF_ECP_STS_MASK 0x1ffu 80 #define MCHP_SAF_ECP_STS_ERR_MASK 0x1fcu 81 #define MCHP_SAF_ECP_STS_DONE BIT(0) 82 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1) 83 #define MCHP_SAF_ECP_STS_TMOUT BIT(2) 84 #define MCHP_SAF_ECP_STS_OOR BIT(3) 85 #define MCHP_SAF_ECP_STS_AV BIT(4) 86 #define MCHP_SAF_ECP_STS_BND_4K BIT(5) 87 #define MCHP_SAF_ECP_STS_ERSZ BIT(6) 88 #define MCHP_SAF_ECP_STS_ST_OVFL BIT(7) 89 #define MCHP_SAF_ECP_STS_BAD_REQ BIT(8) 90 91 /* SAF EC Portal Interrupt Enable register */ 92 #define MCHP_SAF_ECP_INTEN_OFS 0x2cu 93 #define MCHP_SAF_ECP_INTEN_MASK 0x01u 94 #define MCHP_SAF_ECP_INTEN_DONE BIT(0) 95 96 /* SAF Flash Configuratin Size Limit register */ 97 #define MCHP_SAF_FL_CFG_SIZE_LIM_OFS 0x30u 98 #define MCHP_SAF_FL_CFG_SIZE_LIM_MASK 0xffffffffu 99 100 /* SAF Flash Configuration Threshold register */ 101 #define MCHP_SAF_FL_CFG_THRH_OFS 0x34u 102 #define MCHP_SAF_FL_CFG_THRH_MASK 0xffffffffu 103 104 /* SAF Flash Configuration Miscellaneous register */ 105 #define MCHP_SAF_FL_CFG_MISC_OFS 0x38u 106 #define MCHP_SAF_FL_CFG_MISC_MASK 0x000030f3u 107 #define MCHP_SAF_FL_CFG_MISC_PFOE_MASK 0x03u 108 #define MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 0x00u 109 #define MCHP_SAF_FL_CFG_MISC_PFOE_EXP 0x03u 110 #define MCHP_SAF_FL_CFG_MISC_CS0_4BM BIT(4) 111 #define MCHP_SAF_FL_CFG_MISC_CS1_4BM BIT(5) 112 #define MCHP_SAF_FL_CFG_MISC_CS0_CPE BIT(6) 113 #define MCHP_SAF_FL_CFG_MISC_CS1_CPE BIT(7) 114 #define MCHP_SAF_FL_CFG_MISC_SAF_EN BIT(12) 115 #define MCHP_SAF_FL_CFG_MISC_SAF_LOCK BIT(13) 116 117 /* SAF eSPI Monitor Status register */ 118 #define MCHP_SAF_ESPI_MON_STATUS_OFS 0x3cu 119 #define MCHP_SAF_ESPI_MON_STATUS_MASK 0x1fu 120 #define MCHP_SAF_ESPI_MON_STS_TMOUT BIT(0) 121 #define MCHP_SAF_ESPI_MON_STS_OOR BIT(1) 122 #define MCHP_SAF_ESPI_MON_STS_AV BIT(2) 123 #define MCHP_SAF_ESPI_MON_STS_BND_4K BIT(3) 124 #define MCHP_SAF_ESPI_MON_STS_ERSZ BIT(4) 125 126 /* SAF eSPI Monitor Interrupt Enable register */ 127 #define MCHP_SAF_ESPI_MON_INTEN_OFS 0x40u 128 #define MCHP_SAF_ESPI_MON_INTEN_MASK 0x1fu 129 #define MCHP_SAF_ESPI_MON_INTEN_TMOUT BIT(0) 130 #define MCHP_SAF_ESPI_MON_INTEN_OOR BIT(1) 131 #define MCHP_SAF_ESPI_MON_INTEN_AV BIT(2) 132 #define MCHP_SAF_ESPI_MON_INTEN_BND_4K BIT(3) 133 #define MCHP_SAF_ESPI_MON_INTEN_ERSZ BIT(4) 134 135 /* SAF EC Portal Busy register */ 136 #define MCHP_SAF_ECP_BUSY_OFS 0x44u 137 #define MCHP_SAF_ECP_BUSY_MASK 0x01u 138 #define MCHP_SAF_ECP_BUSY BIT(0) 139 140 /* SAF CS0/CS1 Opcode A registers */ 141 #define MCHP_SAF_CS0_OPA_OFS 0x4cu 142 #define MCHP_SAF_CS1_OPA_OFS 0x5cu 143 #define MCHP_SAF_CS_OPA_MASK 0xffffffffu 144 #define MCHP_SAF_CS_OPA_WE_POS 0 145 #define MCHP_SAF_CS_OPA_WE_MASK 0xfful 146 #define MCHP_SAF_CS_OPA_SUS_POS 8 147 #define MCHP_SAF_CS_OPA_SUS_MASK 0xff00ul 148 #define MCHP_SAF_CS_OPA_RSM_POS 16 149 #define MCHP_SAF_CS_OPA_RSM_MASK 0xff0000ul 150 #define MCHP_SAF_CS_OPA_POLL1_POS 24 151 #define MCHP_SAF_CS_OPA_POLL1_MASK 0xff000000ul 152 153 /* SAF CS0/CS1 Opcode B registers */ 154 #define MCHP_SAF_CS0_OPB_OFS 0x50u 155 #define MCHP_SAF_CS1_OPB_OFS 0x60u 156 #define MCHP_SAF_CS_OPB_OFS 0xffffffffu 157 #define MCHP_SAF_CS_OPB_ER0_POS 0 158 #define MCHP_SAF_CS_OPB_ER0_MASK 0xffu 159 #define MCHP_SAF_CS_OPB_ER1_POS 8 160 #define MCHP_SAF_CS_OPB_ER1_MASK 0xff00ul 161 #define MCHP_SAF_CS_OPB_ER2_POS 16 162 #define MCHP_SAF_CS_OPB_ER2_MASK 0xff0000ul 163 #define MCHP_SAF_CS_OPB_PGM_POS 24 164 #define MCHP_SAF_CS_OPB_PGM_MASK 0xff000000ul 165 166 /* SAF CS0/CS1 Opcode C registers */ 167 #define MCHP_SAF_CS0_OPC_OFS 0x54u 168 #define MCHP_SAF_CS1_OPC_OFS 0x64u 169 #define MCHP_SAF_CS_OPC_MASK 0xffffffffu 170 #define MCHP_SAF_CS_OPC_RD_POS 0 171 #define MCHP_SAF_CS_OPC_RD_MASK 0xffu 172 #define MCHP_SAF_CS_OPC_MNC_POS 8 173 #define MCHP_SAF_CS_OPC_MNC_MASK 0xff00ul 174 #define MCHP_SAF_CS_OPC_MC_POS 16 175 #define MCHP_SAF_CS_OPC_MC_MASK 0xff0000ul 176 #define MCHP_SAF_CS_OPC_POLL2_POS 24 177 #define MCHP_SAF_CS_OPC_POLL2_MASK 0xff000000ul 178 179 /* SAF CS0/CS1 registers */ 180 #define MCHP_SAF_CS0_DESCR_OFS 0x58u 181 #define MCHP_SAF_CS1_DESCR_OFS 0x68u 182 #define MCHP_SAF_CS_DESCR_MASK 0x0000ff0fu 183 #define MCHP_SAF_CS_DESCR_ENTC_POS 0 184 #define MCHP_SAF_CS_DESCR_ENTC_MASK 0x0fu 185 #define MCHP_SAF_CS_DESCR_RDC_POS 8 186 #define MCHP_SAF_CS_DESCR_RDC_MASK 0x0f00ul 187 #define MCHP_SAF_CS_DESCR_SZC_POS 12 188 #define MCHP_SAF_CS_DESCR_SZC_MASK 0xf000ul 189 190 /* SAF Flash Configuration General Descriptors register */ 191 #define MCHP_SAF_FL_CFG_GEN_DESCR_OFS 0x6cu 192 #define MCHP_SAF_FL_CFG_GEN_DESCR_MASK 0x0000ff0fu 193 /* value for standard 16 descriptor programming */ 194 #define MCHP_SAF_FL_CFG_GEN_DESCR_STD 0x0000ee0cu 195 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_POS 0 196 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_MASK 0x0fu 197 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS 8 198 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_MASK \ 199 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS) 200 201 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS 12 202 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_MASK \ 203 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS) 204 205 /* SAF Protection Lock register */ 206 #define MCHP_SAF_PROT_LOCK_OFS 0x70u 207 #define MCHP_SAF_PROT_LOCK_MASK 0x1ffffu 208 #define MCHP_SAF_PROT_LOCK0 BIT(0) 209 #define MCHP_SAF_PROT_LOCK1 BIT(1) 210 #define MCHP_SAF_PROT_LOCK2 BIT(2) 211 #define MCHP_SAF_PROT_LOCK3 BIT(3) 212 #define MCHP_SAF_PROT_LOCK4 BIT(4) 213 #define MCHP_SAF_PROT_LOCK5 BIT(5) 214 #define MCHP_SAF_PROT_LOCK6 BIT(6) 215 #define MCHP_SAF_PROT_LOCK7 BIT(7) 216 #define MCHP_SAF_PROT_LOCK8 BIT(8) 217 #define MCHP_SAF_PROT_LOCK9 BIT(9) 218 #define MCHP_SAF_PROT_LOCK10 BIT(10) 219 #define MCHP_SAF_PROT_LOCK11 BIT(11) 220 #define MCHP_SAF_PROT_LOCK12 BIT(12) 221 #define MCHP_SAF_PROT_LOCK13 BIT(13) 222 #define MCHP_SAF_PROT_LOCK14 BIT(14) 223 #define MCHP_SAF_PROT_LOCK15 BIT(15) 224 #define MCHP_SAF_PROT_LOCK16 BIT(16) 225 226 /* SAF Protection Dirty register */ 227 #define MCHP_SAF_PROT_DIRTY_OFS 0x74u 228 #define MCHP_SAF_PROT_DIRTY_MASK 0xfffu 229 #define MCHP_SAF_PROT_DIRTY0 BIT(0) 230 #define MCHP_SAF_PROT_DIRTY1 BIT(1) 231 #define MCHP_SAF_PROT_DIRTY2 BIT(2) 232 #define MCHP_SAF_PROT_DIRTY3 BIT(3) 233 #define MCHP_SAF_PROT_DIRTY4 BIT(4) 234 #define MCHP_SAF_PROT_DIRTY5 BIT(5) 235 #define MCHP_SAF_PROT_DIRTY6 BIT(6) 236 #define MCHP_SAF_PROT_DIRTY7 BIT(7) 237 #define MCHP_SAF_PROT_DIRTY8 BIT(8) 238 #define MCHP_SAF_PROT_DIRTY9 BIT(9) 239 #define MCHP_SAF_PROT_DIRTY10 BIT(10) 240 #define MCHP_SAF_PROT_DIRTY11 BIT(11) 241 242 /* SAF Tag Map 0 register */ 243 #define MCHP_SAF_TAG_MAP0_OFS 0x78u 244 #define MCHP_SAF_TAG_MAP0_MASK 0x77777777u 245 #define MCHP_SAF_TAG_MAP0_DFLT_VAL 0x23221100u 246 #define MCHP_SAF_TAG_MAP0_STM0_POS 0 247 #define MCHP_SAF_TAG_MAP0_STM0_MASK 0x07u 248 #define MCHP_SAF_TAG_MAP0_STM1_POS 4 249 #define MCHP_SAF_TAG_MAP0_STM1_MASK \ 250 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP0_STM1_POS) 251 #define MCHP_SAF_TAG_MAP0_STM2_POS 8 252 #define MCHP_SAF_TAG_MAP0_STM2_MASK \ 253 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM2_POS) 254 #define MCHP_SAF_TAG_MAP0_STM3_POS 12 255 #define MCHP_SAF_TAG_MAP0_STM3_MASK \ 256 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM3_POS) 257 #define MCHP_SAF_TAG_MAP0_STM4_POS 16 258 #define MCHP_SAF_TAG_MAP0_STM4_MASK \ 259 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM4_POS) 260 #define MCHP_SAF_TAG_MAP0_STM5_POS 20 261 #define MCHP_SAF_TAG_MAP0_STM5_MASK \ 262 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM5_POS) 263 #define MCHP_SAF_TAG_MAP0_STM6_POS 24 264 #define MCHP_SAF_TAG_MAP0_STM6_MASK \ 265 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM6_POS) 266 #define MCHP_SAF_TAG_MAP0_STM7_POS 28 267 #define MCHP_SAF_TAG_MAP0_STM7_MASK \ 268 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM7_POS) 269 270 /* SAF Tag Map 1 register */ 271 #define MCHP_SAF_TAG_MAP1_OFS 0x7Cu 272 #define MCHP_SAF_TAG_MAP1_MASK 0x77777777u 273 #define MCHP_SAF_TAG_MAP1_DFLT_VAL 0x77677767u 274 #define MCHP_SAF_TAG_MAP1_STM8_POS 0 275 #define MCHP_SAF_TAG_MAP1_STM8_MASK 0x07u 276 #define MCHP_SAF_TAG_MAP1_STM9_POS 4 277 #define MCHP_SAF_TAG_MAP1_STM9_MASK \ 278 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STM9_POS) 279 #define MCHP_SAF_TAG_MAP1_STMA_POS 8 280 #define MCHP_SAF_TAG_MAP1_STMA_MASK \ 281 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMA_POS) 282 #define MCHP_SAF_TAG_MAP1_STMB_POS 12 283 #define MCHP_SAF_TAG_MAP1_STMB_MASK \ 284 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMB_POS) 285 #define MCHP_SAF_TAG_MAP1_STMC_POS 16 286 #define MCHP_SAF_TAG_MAP1_STMC_MASK \ 287 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMC_POS) 288 #define MCHP_SAF_TAG_MAP1_STMD_POS 20 289 #define MCHP_SAF_TAG_MAP1_STMD_MASK \ 290 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMD_POS) 291 #define MCHP_SAF_TAG_MAP1_STME_POS 24 292 #define MCHP_SAF_TAG_MAP1_STME_MASK \ 293 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STME_POS) 294 #define MCHP_SAF_TAG_MAP1_STMF_POS 28 295 #define MCHP_SAF_TAG_MAP1_STMF_MASK \ 296 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMF_POS) 297 298 /* SAF Tag Map 2 register */ 299 #define MCHP_SAF_TAG_MAP2_OFS 0x80u 300 #define MCHP_SAF_TAG_MAP2_MASK 0x80000007u 301 #define MCHP_SAF_TAG_MAP2_DFLT_VAL 0x00000005u 302 #define MCHP_SAF_TAG_MAP2_SM_EC_POS 0 303 #define MCHP_SAF_TAG_MAP2_SM_EC_MASK 0x07u 304 #define MCHP_SAF_TAG_MAP2_LOCK_POS 31 305 #define MCHP_SAF_TAG_MAP2_LOCK BIT(MCHP_SAF_TAG_MAP2_LOCK_POS) 306 307 /* SAF Protection Region Start registers */ 308 #define MCHP_SAF_PROT_RG0_START_OFS 0x84u 309 #define MCHP_SAF_PROT_RG1_START_OFS 0x94u 310 #define MCHP_SAF_PROT_RG2_START_OFS 0xA4u 311 #define MCHP_SAF_PROT_RG3_START_OFS 0xB4u 312 #define MCHP_SAF_PROT_RG4_START_OFS 0xC4u 313 #define MCHP_SAF_PROT_RG5_START_OFS 0xD4u 314 #define MCHP_SAF_PROT_RG6_START_OFS 0xE4u 315 #define MCHP_SAF_PROT_RG7_START_OFS 0xF4u 316 #define MCHP_SAF_PROT_RG8_START_OFS 0x104u 317 #define MCHP_SAF_PROT_RG9_START_OFS 0x114u 318 #define MCHP_SAF_PROT_RG10_START_OFS 0x124u 319 #define MCHP_SAF_PROT_RG11_START_OFS 0x134u 320 #define MCHP_SAF_PROT_RG12_START_OFS 0x144u 321 #define MCHP_SAF_PROT_RG13_START_OFS 0x154u 322 #define MCHP_SAF_PROT_RG14_START_OFS 0x164u 323 #define MCHP_SAF_PROT_RG15_START_OFS 0x174u 324 #define MCHP_SAF_PROT_RG16_START_OFS 0x184u 325 #define MCHP_SAF_PROT_RG_START_MASK 0xfffffu 326 #define MCHP_SAF_PROT_RG_START_DFLT 0x07fffu 327 328 /* SAF Protection Region Limit registers */ 329 #define MCHP_SAF_PROT_RG0_LIMIT_OFS 0x88u 330 #define MCHP_SAF_PROT_RG1_LIMIT_OFS 0x98u 331 #define MCHP_SAF_PROT_RG2_LIMIT_OFS 0xa8u 332 #define MCHP_SAF_PROT_RG3_LIMIT_OFS 0xb8u 333 #define MCHP_SAF_PROT_RG4_LIMIT_OFS 0xc8u 334 #define MCHP_SAF_PROT_RG5_LIMIT_OFS 0xd8u 335 #define MCHP_SAF_PROT_RG6_LIMIT_OFS 0xe8u 336 #define MCHP_SAF_PROT_RG7_LIMIT_OFS 0xf8u 337 #define MCHP_SAF_PROT_RG8_LIMIT_OFS 0x108u 338 #define MCHP_SAF_PROT_RG9_LIMIT_OFS 0x118u 339 #define MCHP_SAF_PROT_RG10_LIMIT_OFS 0x128u 340 #define MCHP_SAF_PROT_RG11_LIMIT_OFS 0x138u 341 #define MCHP_SAF_PROT_RG12_LIMIT_OFS 0x148u 342 #define MCHP_SAF_PROT_RG13_LIMIT_OFS 0x158u 343 #define MCHP_SAF_PROT_RG14_LIMIT_OFS 0x168u 344 #define MCHP_SAF_PROT_RG15_LIMIT_OFS 0x178u 345 #define MCHP_SAF_PROT_RG16_LIMIT_OFS 0x188u 346 #define MCHP_SAF_PROT_RG_LIMIT_MASK 0xfffffu 347 #define MCHP_SAF_PROT_RG_LIMIT_DFLT 0 348 349 /* SAF Protection Region Write Bitmap registers */ 350 #define MCHP_SAF_PROT_RG0_WBM_OFS 0x8cu 351 #define MCHP_SAF_PROT_RG1_WBM_OFS 0x9cu 352 #define MCHP_SAF_PROT_RG2_WBM_OFS 0xacu 353 #define MCHP_SAF_PROT_RG3_WBM_OFS 0xbcu 354 #define MCHP_SAF_PROT_RG4_WBM_OFS 0xccu 355 #define MCHP_SAF_PROT_RG5_WBM_OFS 0xdcu 356 #define MCHP_SAF_PROT_RG6_WBM_OFS 0xefu 357 #define MCHP_SAF_PROT_RG7_WBM_OFS 0xfcu 358 #define MCHP_SAF_PROT_RG8_WBM_OFS 0x10cu 359 #define MCHP_SAF_PROT_RG9_WBM_OFS 0x11cu 360 #define MCHP_SAF_PROT_RG10_WBM_OFS 0x12cu 361 #define MCHP_SAF_PROT_RG11_WBM_OFS 0x13cu 362 #define MCHP_SAF_PROT_RG12_WBM_OFS 0x14cu 363 #define MCHP_SAF_PROT_RG13_WBM_OFS 0x15cu 364 #define MCHP_SAF_PROT_RG14_WBM_OFS 0x16cu 365 #define MCHP_SAF_PROT_RG15_WBM_OFS 0x17cu 366 #define MCHP_SAF_PROT_RG16_WBM_OFS 0x18cu 367 #define MCHP_SAF_PROT_RG_WBM_MASK 0xffu 368 #define MCHP_SAF_PROT_RG_WBM0 BIT(0) 369 #define MCHP_SAF_PROT_RG_WBM1 BIT(1) 370 #define MCHP_SAF_PROT_RG_WBM2 BIT(2) 371 #define MCHP_SAF_PROT_RG_WBM3 BIT(3) 372 #define MCHP_SAF_PROT_RG_WBM4 BIT(4) 373 #define MCHP_SAF_PROT_RG_WBM5 BIT(5) 374 #define MCHP_SAF_PROT_RG_WBM6 BIT(6) 375 #define MCHP_SAF_PROT_RG_WBM7 BIT(7) 376 377 /* SAF Protection Region Read Bitmap registers */ 378 #define MCHP_SAF_PROT_RG0_RBM_OFS 0x90u 379 #define MCHP_SAF_PROT_RG1_RBM_OFS 0xa0u 380 #define MCHP_SAF_PROT_RG2_RBM_OFS 0xb0u 381 #define MCHP_SAF_PROT_RG3_RBM_OFS 0xc0u 382 #define MCHP_SAF_PROT_RG4_RBM_OFS 0xd0u 383 #define MCHP_SAF_PROT_RG5_RBM_OFS 0xe0u 384 #define MCHP_SAF_PROT_RG6_RBM_OFS 0xf0u 385 #define MCHP_SAF_PROT_RG7_RBM_OFS 0x100u 386 #define MCHP_SAF_PROT_RG8_RBM_OFS 0x110u 387 #define MCHP_SAF_PROT_RG9_RBM_OFS 0x120u 388 #define MCHP_SAF_PROT_RG10_RBM_OFS 0x130u 389 #define MCHP_SAF_PROT_RG11_RBM_OFS 0x140u 390 #define MCHP_SAF_PROT_RG12_RBM_OFS 0x150u 391 #define MCHP_SAF_PROT_RG13_RBM_OFS 0x160u 392 #define MCHP_SAF_PROT_RG14_RBM_OFS 0x170u 393 #define MCHP_SAF_PROT_RG15_RBM_OFS 0x180u 394 #define MCHP_SAF_PROT_RG16_RBM_OFS 0x190u 395 #define MCHP_SAF_PROT_RG_RBM_MASK 0xffu 396 #define MCHP_SAF_PROT_RG_RBM0 BIT(0) 397 #define MCHP_SAF_PROT_RG_RBM1 BIT(1) 398 #define MCHP_SAF_PROT_RG_RBM2 BIT(2) 399 #define MCHP_SAF_PROT_RG_RBM3 BIT(3) 400 #define MCHP_SAF_PROT_RG_RBM4 BIT(4) 401 #define MCHP_SAF_PROT_RG_RBM5 BIT(5) 402 #define MCHP_SAF_PROT_RG_RBM6 BIT(6) 403 #define MCHP_SAF_PROT_RG_RBM7 BIT(7) 404 405 /* SAF Poll Timeout register */ 406 #define MCHP_SAF_POLL_TMOUT_OFS 0x194u 407 #define MCHP_SAF_POLL_TMOUT_MASK 0x3ffffu 408 #define MCHP_SAF_POLL_TMOUT_5S 0x28000u 409 410 /* SAF Poll Interval register */ 411 #define MCHP_SAF_POLL_INTRVL_OFS 0x198u 412 #define MCHP_SAF_POLL_INTRVL_MASK 0xffffu 413 414 /* SAF Suspend Resume Interval register */ 415 #define MCHP_SAF_SUS_RSM_INTRVL_OFS 0x19Cu 416 #define MCHP_SAF_SUS_RSM_INTRVL_MASK 0xffffu 417 418 /* SAF Consecutive Read Timeout register */ 419 #define MCHP_SAF_CRD_TMOUT_OFS 0x1a0u 420 #define MCHP_SAF_CRD_TMOUT_MASK 0xfffffu 421 422 /* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */ 423 #define MCHP_SAF_FL0_CFG_P2M_OFS 0x1a4u 424 #define MCHP_SAF_FL1_CFG_P2M_OFS 0x1a6u 425 #define MCHP_SAF_FL_CFG_P2M_MASK 0xffffu 426 427 /* SAF Flash Configuration Special Mode register */ 428 #define MCHP_SAF_FL_CFG_SPM_OFS 0x1a8u 429 #define MCHP_SAF_FL_CFG_SPM_MASK 0x01u 430 #define MCHP_SAF_FL_CFG_SPM_DIS_SUSP BIT(0) 431 432 /* SAF Suspend Check Delay register */ 433 #define MCHP_SAF_SUS_CHK_DLY_OFS 0x1acu 434 #define MCHP_SAF_SUS_CHK_DLY_MASK 0xfffffu 435 436 /* SAF Flash 0/1 Continuous Mode Prefix registers */ 437 #define MCHP_SAF_FL_CM_PRF_OFS 0x1b0u 438 #define MCHP_SAF_FL_CM_PRF_MASK 0xffffu 439 #define MCHP_SAF_FL_CM_PRF_CS_OP_POS 0 440 #define MCHP_SAF_FL_CM_PRF_CS_OP_MASK 0xffu 441 #define MCHP_SAF_FL_CM_PRF_CS_DAT_POS 8 442 #define MCHP_SAF_FL_CM_PRF_CS_DAT_MASK \ 443 SHLU32(MCHP_SAF_FL_CM_PRF_CS_OP_MASK, MCHP_SAF_FL_CM_PRF_CS_DAT_POS) 444 445 /* SAF DnX Protection Bypass register */ 446 #define MCHP_SAF_DNX_PROT_BYP_OFS 0x1b4u 447 #define MCHP_SAF_DNX_PROT_BYP_MASK 0xffffffffu 448 449 /* SAF Communication Mode */ 450 #define MCHP_SAF_COMM_MODE_MASK 0x01u 451 /* Allow pre-fetch from flash devices */ 452 #define MCHP_SAF_COMM_MODE_PF_EN BIT(0) 453 454 /* SAF TAG numbers[0:0xF] */ 455 #define MCHP_SAF_TAG_M0T0 0u 456 #define MCHP_SAF_TAG_M0T1 1u 457 #define MCHP_SAF_TAG_M1T0 2u 458 #define MCHP_SAF_TAG_M1T1 3u 459 #define MCHP_SAF_TAG_M2T0 4u 460 #define MCHP_SAF_TAG_M2T1 5u 461 #define MCHP_SAF_TAG_M3T0 6u 462 #define MCHP_SAF_TAG_M2T2 7u 463 #define MCHP_SAF_TAG_M6T0 9u 464 #define MCHP_SAF_TAG_M6T1 0x0du 465 #define MCHP_SAF_TAG_MAX 0x10u 466 467 /* SAF Master numbers */ 468 #define MCHP_SAF_MSTR_CS_INIT 0u 469 #define MCHP_SAF_MSTR_CPU 1u 470 #define MCHP_SAF_MSTR_CS_ME 2u 471 #define MCHP_SAF_MSTR_CS_LAN 3u 472 #define MCHP_SAF_MSTR_UNUSED4 4u 473 #define MCHP_SAF_MSTR_EC_FW 5u 474 #define MCHP_SAF_MSTR_CS_IE 6u 475 #define MCHP_SAF_MSTR_UNUSED7 7u 476 #define MCHP_SAF_MSTR_MAX 8u 477 #define MCHP_SAF_MSTR_ALL 0xffu 478 479 /* eSPI SAF */ 480 /** @brief SAF SPI Opcodes and descriptor indices */ 481 struct mchp_espi_saf_op { 482 volatile uint32_t OPA; 483 volatile uint32_t OPB; 484 volatile uint32_t OPC; 485 volatile uint32_t OP_DESCR; 486 }; 487 488 /** @brief SAF protection regions contain 4 32-bit registers. */ 489 struct mchp_espi_saf_pr { 490 volatile uint32_t START; 491 volatile uint32_t LIMIT; 492 volatile uint32_t WEBM; 493 volatile uint32_t RDBM; 494 }; 495 496 /** @brief eSPI SAF configuration and control registers at 0x40008000 */ 497 struct mchp_espi_saf { 498 uint32_t RSVD1[6]; 499 volatile uint32_t SAF_ECP_CMD; 500 volatile uint32_t SAF_ECP_FLAR; 501 volatile uint32_t SAF_ECP_START; 502 volatile uint32_t SAF_ECP_BFAR; 503 volatile uint32_t SAF_ECP_STATUS; 504 volatile uint32_t SAF_ECP_INTEN; 505 volatile uint32_t SAF_FL_CFG_SIZE_LIM; 506 volatile uint32_t SAF_FL_CFG_THRH; 507 volatile uint32_t SAF_FL_CFG_MISC; 508 volatile uint32_t SAF_ESPI_MON_STATUS; 509 volatile uint32_t SAF_ESPI_MON_INTEN; 510 volatile uint32_t SAF_ECP_BUSY; 511 uint32_t RSVD2[1]; 512 struct mchp_espi_saf_op SAF_CS_OP[2]; 513 volatile uint32_t SAF_FL_CFG_GEN_DESCR; 514 volatile uint32_t SAF_PROT_LOCK; 515 volatile uint32_t SAF_PROT_DIRTY; 516 volatile uint32_t SAF_TAG_MAP[3]; 517 struct mchp_espi_saf_pr SAF_PROT_RG[17]; 518 volatile uint32_t SAF_POLL_TMOUT; 519 volatile uint32_t SAF_POLL_INTRVL; 520 volatile uint32_t SAF_SUS_RSM_INTRVL; 521 volatile uint32_t SAF_CONSEC_RD_TMOUT; 522 volatile uint16_t SAF_CS0_CFG_P2M; 523 volatile uint16_t SAF_CS1_CFG_P2M; 524 volatile uint32_t SAF_FL_CFG_SPM; 525 volatile uint32_t SAF_SUS_CHK_DLY; 526 volatile uint16_t SAF_CS0_CM_PRF; 527 volatile uint16_t SAF_CS1_CM_PRF; 528 volatile uint32_t SAF_DNX_PROT_BYP; 529 }; 530 531 struct mchp_espi_saf_comm { /* @ 0x40071000 */ 532 uint32_t TEST0; 533 uint32_t TEST1; 534 uint32_t TEST2; 535 uint32_t TEST3; 536 uint32_t TEST4; 537 uint32_t TEST5; 538 uint32_t TEST6; 539 uint32_t RSVD1[(0x2b8 - 0x01c) / 4]; 540 uint32_t SAF_COMM_MODE; /* @ 0x400712b8 */ 541 uint32_t TEST7; 542 }; 543 544 #endif /* _MEC172X_ESPI_SAF_H_ */ 545
