1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_QSPI_H_ 8 #define _MEC_QSPI_H_ 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define QMPSPI_HW_VER 4u 14 15 #define MCHP_QMSPI_BASE_ADDR 0x40070000u 16 17 #define MCHP_QMSPI_MAX_DESCR 16u 18 19 #define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000u 20 #define MCHP_QMSPI_MAX_FREQ_KHZ \ 21 ((MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ) / 1000u) 22 #define MCHP_QMSPI_MIN_FREQ_KHZ (MCHP_QMSPI_MAX_FREQ_KHZ / 256u) 23 24 /* Mode 0: Clock idle = Low. Data change falling edge, sample rising edge */ 25 #define MCHP_QMSPI_SPI_MODE0 0u 26 /* Mode 1: Clock idle = Low. Data change rising edge, sample falling edge */ 27 #define MCHP_QMSPI_SPI_MODE1 0x06u 28 /* Mode 2: Clock idle = High. Data change rising edge, sample falling edge */ 29 #define MCHP_QMSPI_SPI_MODE2 0x06u 30 /* Mode 3: Clock idle = High. Data change falling edge, sample rising edge */ 31 #define MCHP_QMSPI_SPI_MODE3 0x07u 32 33 /* Device ID used in DMA channel Control.DeviceID field */ 34 #define MCHP_QMSPI_TX_DMA_REQ_ID 10u 35 #define MCHP_QMSPI_RX_DMA_REQ_ID 11u 36 37 /* QMSPI transmit and receive FIFO lengths */ 38 #define MCHP_QMSPI_TX_FIFO_LEN 8u 39 #define MCHP_QMSPI_RX_FIFO_LEN 8u 40 41 /* QMSPI Local DMA channels */ 42 #define MCHP_QMSPI_LDMA_RX_CHANNELS 3u 43 #define MCHP_QMSPI_LDMA_TX_CHANNELS 3u 44 45 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u 46 #define MCHP_QMSPI_M_SPI_MODE_OFS 1u 47 #define MCHP_QMSPI_M_CLK_DIV_OFS 2u 48 #define MCHP_QMSPI_CTRL_OFS 4u 49 #define MCHP_QMSPI_EXE_OFS 8u 50 #define MCHP_QMSPI_IF_CTRL_OFS 0x0cu 51 #define MCHP_QMSPI_STS_OFS 0x10u 52 #define MCHP_QMSPI_BUF_CNT_STS_OFS 0x14u 53 #define MCHP_QMSPI_IEN_OFS 0x18u 54 #define MCHP_QMSPI_BUF_CNT_TRIG_OFS 0x1cu 55 #define MCHP_QMSPI_TX_FIFO_OFS 0x20u 56 #define MCHP_QMSPI_RX_FIFO_OFS 0x24u 57 #define MCHP_QMSPI_CSTM_OFS 0x28u 58 /* 0 <= n < MCHP_QMSPI_MAX_DESCR */ 59 #define MCHP_QMSPI_DESC0_OFS 0x30u 60 #define MCHP_QMSPI_DESCR_OFS(n) (0x30u + ((uint32_t)(n) * 4u)) 61 #define MCHP_QMSPI_ALIAS_CTRL_OFS 0xb0u 62 #define MCHP_QMSPI_MODE_ALT1_OFS 0xc0u 63 #define MCHP_QMSPI_TAPS_OFS 0xd0u 64 #define MCHP_QMSPI_TAPS_ADJ_OFS 0xd4u 65 #define MCHP_QMSPI_TAPS_CTRL_OFS 0xd8u 66 #define MCHP_QMSPI_LDMA_RX_EN_OFS 0x100u 67 #define MCHP_QMSPI_LDMA_TX_EN_OFS 0x104u 68 #define MCHP_QMSPI_LDMA_RX_0_CTRL_OFS 0x110u 69 #define MCHP_QMSPI_LDMA_RX_0_START_OFS 0x114u 70 #define MCHP_QMSPI_LDMA_RX_0_LEN_OFS 0x118u 71 #define MCHP_QMSPI_LDMA_RX_1_CTRL_OFS 0x120u 72 #define MCHP_QMSPI_LDMA_RX_1_START_OFS 0x124u 73 #define MCHP_QMSPI_LDMA_RX_1_LEN_OFS 0x128u 74 #define MCHP_QMSPI_LDMA_RX_2_CTRL_OFS 0x130u 75 #define MCHP_QMSPI_LDMA_RX_2_START_OFS 0x134u 76 #define MCHP_QMSPI_LDMA_RX_2_LEN_OFS 0x138u 77 #define MCHP_QMSPI_LDMA_TX_0_CTRL_OFS 0x140u 78 #define MCHP_QMSPI_LDMA_TX_0_START_OFS 0x144u 79 #define MCHP_QMSPI_LDMA_TX_0_LEN_OFS 0x148u 80 #define MCHP_QMSPI_LDMA_TX_1_CTRL_OFS 0x150u 81 #define MCHP_QMSPI_LDMA_TX_1_START_OFS 0x154u 82 #define MCHP_QMSPI_LDMA_TX_1_LEN_OFS 0x158u 83 #define MCHP_QMSPI_LDMA_TX_2_CTRL_OFS 0x160u 84 #define MCHP_QMSPI_LDMA_TX_2_START_OFS 0x164u 85 #define MCHP_QMSPI_LDMA_TX_2_LEN_OFS 0x168u 86 87 #define MCHP_QMSPI_MODE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x00) 88 #define MCHP_QMSPI_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x04) 89 #define MCHP_QMSPI_EXE_ADDR (MCHP_QMSPI_BASE_ADDR + 0x08) 90 #define MCHP_QMSPI_IFC_ADDR (MCHP_QMSPI_BASE_ADDR + 0x0c) 91 #define MCHP_QMSPI_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x10) 92 #define MCHP_QMSPI_BUFCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) 93 #define MCHP_QMSPI_TX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x14) 94 #define MCHP_QMSPI_RX_BCNT_STS_ADDR (MCHP_QMSPI_BASE_ADDR + 0x16) 95 #define MCHP_QMSPI_IEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x18) 96 #define MCHP_QMSPI_TXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x20) 97 #define MCHP_QMSPI_RXB_ADDR (MCHP_QMSPI_BASE_ADDR + 0x24) 98 #define MCHP_QMSPI_CSTM_ADDR (MCHP_QMSPI_BASE_ADDR + 0x28) 99 #define MCHP_QMSPI_DESCR_ADDR(n) \ 100 (MCHP_QMSPI_BASE_ADDR + (0x30 + (((uint32_t)(n) & 0x0Fu) << 2))) 101 102 #define MCHP_QMSPI_ALIAS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xb0u) 103 #define MCHP_QMSPI_MODE_ALT1_ADDR (MCHP_QMSPI_BASE_ADDR + 0xc0u) 104 #define MCHP_QMSPI_TAPS_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd0u) 105 #define MCHP_QMSPI_TAPS_ADJ_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd4u) 106 #define MCHP_QMSPI_TAPS_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0xd8u) 107 #define MCHP_QMSPI_LDMA_RX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x100u) 108 #define MCHP_QMSPI_LDMA_TX_EN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x104u) 109 #define MCHP_QMSPI_LDMA_RX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x110u) 110 #define MCHP_QMSPI_LDMA_RX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x114u) 111 #define MCHP_QMSPI_LDMA_RX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x118u) 112 #define MCHP_QMSPI_LDMA_RX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x120u) 113 #define MCHP_QMSPI_LDMA_RX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x124u) 114 #define MCHP_QMSPI_LDMA_RX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x128u) 115 #define MCHP_QMSPI_LDMA_RX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x130u) 116 #define MCHP_QMSPI_LDMA_RX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x134u) 117 #define MCHP_QMSPI_LDMA_RX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x138u) 118 #define MCHP_QMSPI_LDMA_TX_0_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x140u) 119 #define MCHP_QMSPI_LDMA_TX_0_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x144u) 120 #define MCHP_QMSPI_LDMA_TX_0_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x148u) 121 #define MCHP_QMSPI_LDMA_TX_1_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x150u) 122 #define MCHP_QMSPI_LDMA_TX_1_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x154u) 123 #define MCHP_QMSPI_LDMA_TX_1_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x158u) 124 #define MCHP_QMSPI_LDMA_TX_2_CTRL_ADDR (MCHP_QMSPI_BASE_ADDR + 0x160u) 125 #define MCHP_QMSPI_LDMA_TX_2_START_ADDR (MCHP_QMSPI_BASE_ADDR + 0x164u) 126 #define MCHP_QMSPI_LDMA_TX_2_LEN_ADDR (MCHP_QMSPI_BASE_ADDR + 0x168u) 127 128 /* Mode Register */ 129 #define MCHP_QMSPI_M_MASK 0x00ff371fu 130 #define MCHP_QMSPI_M_ACTIVATE BIT(0) 131 #define MCHP_QMSPI_M_SRST BIT(1) 132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2) 133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3) 134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4) 135 #define MCHP_QMSPI_M_CPOL_POS 8u 136 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_LO 0 137 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8) 138 139 #define MCHP_QMSPI_M_CPHA_MOSI_POS 9u 140 /* MOSI data changes on first clock edge of clock pulse */ 141 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 0u 142 /* MOSI data changes on second clock edge of clock pulse */ 143 #define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9) 144 145 #define MCHP_QMSPI_M_CPHA_MIS0_POS 10u 146 /* MISO data capture on first clock edge of clock pulse */ 147 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u 148 /* MISO data capture on second clock edge of clock pulse */ 149 #define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10) 150 151 #define MCHP_QMSPI_M_SIG_POS 8u 152 #define MCHP_QMSPI_M_SIG_MASK0 0x07u 153 #define MCHP_QMSPI_M_SIG_MASK 0x0700u 154 #define MCHP_QMSPI_M_SIG_MODE0_VAL 0u 155 #define MCHP_QMSPI_M_SIG_MODE1_VAL 0x06u 156 #define MCHP_QMSPI_M_SIG_MODE2_VAL 0x01u 157 #define MCHP_QMSPI_M_SIG_MODE3_VAL 0x07u 158 #define MCHP_QMSPI_M_SIG_MODE0 0u 159 #define MCHP_QMSPI_M_SIG_MODE1 SHLU32(6u, MCHP_QMSPI_M_SIG_POS) 160 #define MCHP_QMSPI_M_SIG_MODE2 SHLU32(1u, MCHP_QMSPI_M_SIG_POS) 161 #define MCHP_QMSPI_M_SIG_MODE3 SHLU32(7u, MCHP_QMSPI_M_SIG_POS) 162 #define MCHP_QMSPI_M_CS_POS 12u 163 #define MCHP_QMSPI_M_CS_MASK0 0x03u 164 #define MCHP_QMSPI_M_CS_MASK SHLU32(3u, 12) 165 #define MCHP_QMSPI_M_CS0 SHLU32(0u, 12) 166 #define MCHP_QMSPI_M_CS1 SHLU32(1u, 12) 167 /* Two chip selects only 0 and 1 */ 168 #define MCHP_QMSPI_M_CS(n) \ 169 (((uint32_t)(n) & MCHP_QMSPI_M_CS_MASK0) << MCHP_QMSPI_M_CS_POS) 170 #define MCHP_QMSPI_M_FDIV_POS 16u 171 #define MCHP_QMSPI_M_FDIV_MASK0 0xffu 172 #define MCHP_QMSPI_M_FDIV_MASK 0x00ff0000u 173 174 /* Control/Descriptors */ 175 #define MCHP_QMSPI_C_IFM_MASK 0x03u 176 #define MCHP_QMSPI_C_IFM_1X 0u 177 #define MCHP_QMSPI_C_IFM_2X 1u 178 #define MCHP_QMSPI_C_IFM_4X 2u 179 #define MCHP_QMSPI_C_TX_POS 2u 180 #define MCHP_QMSPI_C_TX_MASK SHLU32(3u, MCHP_QMSPI_C_TX_POS) 181 #define MCHP_QMSPI_C_TX_DIS 0u 182 #define MCHP_QMSPI_C_TX_DATA SHLU32(1u, MCHP_QMSPI_C_TX_POS) 183 #define MCHP_QMSPI_C_TX_ZEROS SHLU32(2u, MCHP_QMSPI_C_TX_POS) 184 #define MCHP_QMSPI_C_TX_ONES SHLU32(3u, MCHP_QMSPI_C_TX_POS) 185 #define MCHP_QMSPI_C_TX_DMA_POS 4u 186 #define MCHP_QMSPI_C_TX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS) 187 #define MCHP_QMSPI_C_TX_DMA_DIS 0u 188 #define MCHP_QMSPI_C_TX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_TX_DMA_POS) 189 #define MCHP_QMSPI_C_TX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_TX_DMA_POS) 190 #define MCHP_QMSPI_C_TX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_TX_DMA_POS) 191 #define MCHP_QMSPI_C_RX_POS 6u 192 #define MCHP_QMSPI_C_RX_DIS 0u 193 #define MCHP_QMSPI_C_RX_EN BIT(MCHP_QMSPI_C_RX_POS) 194 #define MCHP_QMSPI_C_RX_DMA_POS 7u 195 #define MCHP_QMSPI_C_RX_DMA_MASK SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS) 196 #define MCHP_QMSPI_C_RX_DMA_DIS 0u 197 #define MCHP_QMSPI_C_RX_DMA_1B SHLU32(1u, MCHP_QMSPI_C_RX_DMA_POS) 198 #define MCHP_QMSPI_C_RX_DMA_2B SHLU32(2u, MCHP_QMSPI_C_RX_DMA_POS) 199 #define MCHP_QMSPI_C_RX_DMA_4B SHLU32(3u, MCHP_QMSPI_C_RX_DMA_POS) 200 #define MCHP_QMSPI_C_CLOSE_POS 9u 201 #define MCHP_QMSPI_C_NO_CLOSE 0u 202 #define MCHP_QMSPI_C_CLOSE BIT(MCHP_QMSPI_C_CLOSE_POS) 203 #define MCHP_QMSPI_C_XFR_UNITS_POS 10u 204 #define MCHP_QMSPI_C_XFR_UNITS_MASK SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS) 205 #define MCHP_QMSPI_C_XFR_UNITS_BITS 0u 206 #define MCHP_QMSPI_C_XFR_UNITS_1 SHLU32(1u, MCHP_QMSPI_C_XFR_UNITS_POS) 207 #define MCHP_QMSPI_C_XFR_UNITS_4 SHLU32(2u, MCHP_QMSPI_C_XFR_UNITS_POS) 208 #define MCHP_QMSPI_C_XFR_UNITS_16 SHLU32(3u, MCHP_QMSPI_C_XFR_UNITS_POS) 209 #define MCHP_QMSPI_C_NEXT_DESCR_POS 12u 210 #define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0x0fu 211 #define MCHP_QMSPI_C_NEXT_DESCR_MASK 0xf000u 212 #define MCHP_QMSPI_C_DESCR0 0u 213 #define MCHP_QMSPI_C_DESCR1 0x1000u 214 #define MCHP_QMSPI_C_DESCR2 0x2000u 215 #define MCHP_QMSPI_C_DESCR3 0x3000u 216 #define MCHP_QMSPI_C_DESCR4 0x4000u 217 /* Control register start descriptor field */ 218 #define MCHP_QMSPI_C_DESCR(n) \ 219 SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS) 220 /* Descriptor registers next descriptor field */ 221 #define MCHP_QMSPI_C_NEXT_DESCR(n) \ 222 SHLU32(((n) & 0xFu), MCHP_QMSPI_C_NEXT_DESCR_POS) 223 /* Control register descriptor mode enable */ 224 #define MCHP_QMSPI_C_DESCR_EN_POS 16u 225 #define MCHP_QMSPI_C_DESCR_EN BIT(MCHP_QMSPI_C_DESCR_EN_POS) 226 /* Descriptor registers last descriptor flag */ 227 #define MCHP_QMSPI_C_DESCR_LAST BIT(MCHP_QMSPI_C_DESCR_EN_POS) 228 #define MCHP_QMSPI_C_MAX_UNITS 0x7fffu 229 #define MCHP_QMSPI_C_MAX_UNITS_MASK 0x7fffu 230 #define MCHP_QMSPI_C_XFR_NUNITS_POS 17u 231 #define MCHP_QMSPI_C_XFR_NUNITS_MASK0 0x7fffu 232 #define MCHP_QMSPI_C_XFR_NUNITS_MASK 0xfffe0000u 233 #define MCHP_QMSPI_C_XFR_NUNITS(n) SHLU32((n), MCHP_QMSPI_C_XFR_NUNITS_POS) 234 #define MCHP_QMSPI_C_XFR_NUNITS_GET(descr) ((uint32_t)(descr) >> 17) 235 236 /* Exe */ 237 #define MCHP_QMSPI_EXE_START BIT(0) 238 #define MCHP_QMSPI_EXE_STOP BIT(1) 239 #define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) 240 241 /* Interface Control */ 242 #define MCHP_QMSPI_IFC_DFLT 0u 243 #define MCHP_QMSPI_IFC_WP_OUT_HI BIT(0) 244 #define MCHP_QMSPI_IFC_WP_OUT_EN BIT(1) 245 #define MCHP_QMSPI_IFC_HOLD_OUT_HI BIT(2) 246 #define MCHP_QMSPI_IFC_HOLD_OUT_EN BIT(3) 247 #define MCHP_QMSPI_IFC_PD_ON_NS BIT(4) 248 #define MCHP_QMSPI_IFC_PU_ON_NS BIT(5) 249 #define MCHP_QMSPI_IFC_PD_ON_ND BIT(6) 250 #define MCHP_QMSPI_IFC_PU_ON_ND BIT(7) 251 252 /* Status Register */ 253 #define MCHP_QMSPI_STS_REG_MASK 0x0f01ff1fu 254 #define MCHP_QMSPI_STS_RO_MASK 0x0f013300u 255 #define MCHP_QMSPI_STS_RW1C_MASK 0x0000cc1fu 256 #define MCHP_QMSPI_STS_DONE BIT(0) 257 #define MCHP_QMSPI_STS_DMA_DONE BIT(1) 258 #define MCHP_QMSPI_STS_TXB_ERR BIT(2) 259 #define MCHP_QMSPI_STS_RXB_ERR BIT(3) 260 #define MCHP_QMSPI_STS_PROG_ERR BIT(4) 261 #define MCHP_QMSPI_STS_TXBF_RO BIT(8) 262 #define MCHP_QMSPI_STS_TXBE_RO BIT(9) 263 #define MCHP_QMSPI_STS_TXBR BIT(10) 264 #define MCHP_QMSPI_STS_TXBS BIT(11) 265 #define MCHP_QMSPI_STS_RXBF_RO BIT(12) 266 #define MCHP_QMSPI_STS_RXBE_RO BIT(13) 267 #define MCHP_QMSPI_STS_RXBR BIT(14) 268 #define MCHP_QMSPI_STS_RXBS BIT(15) 269 #define MCHP_QMSPI_STS_ACTIVE_RO BIT(16) 270 #define MCHP_QMSPI_STS_CD_POS 24u 271 #define MCHP_QMSPI_STS_CD_MASK0 0x0fu 272 #define MCHP_QMSPI_STS_CD_MASK 0x0f000000u 273 274 /* Buffer Count Status (RO) */ 275 #define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u 276 #define MCHP_QMSPI_TX_BUF_CNT_STS_MASK 0xffffu 277 #define MCHP_QMSPI_RX_BUF_CNT_STS_POS 16u 278 #define MCHP_QMSPI_RX_BUF_CNT_STS_MASK 0xffff0000u 279 280 /* Interrupt Enable Register */ 281 #define MCHP_QMSPI_IEN_XFR_DONE BIT(0) 282 #define MCHP_QMSPI_IEN_DMA_DONE BIT(1) 283 #define MCHP_QMSPI_IEN_TXB_ERR BIT(2) 284 #define MCHP_QMSPI_IEN_RXB_ERR BIT(3) 285 #define MCHP_QMSPI_IEN_PROG_ERR BIT(4) 286 #define MCHP_QMSPI_IEN_TXB_FULL BIT(8) 287 #define MCHP_QMSPI_IEN_TXB_EMPTY BIT(9) 288 #define MCHP_QMSPI_IEN_TXB_REQ BIT(10) 289 #define MCHP_QMSPI_IEN_RXB_FULL BIT(12) 290 #define MCHP_QMSPI_IEN_RXB_EMPTY BIT(13) 291 #define MCHP_QMSPI_IEN_RXB_REQ BIT(14) 292 293 /* Buffer Count Trigger (RW) */ 294 #define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u 295 #define MCHP_QMSPI_RX_BUF_CNT_TRIG_POS 16u 296 297 /* Chip Select Timing (RW) */ 298 #define MCHP_QMSPI_CSTM_MASK 0xff0f0f0fu 299 #define MCHP_QMSPI_CSTM_DFLT 0x06060406u 300 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u 301 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_MASK 0x0fu 302 #define MCHP_QMSPI_DLY_CK_STP_CS_OFF_POS 8u 303 #define MCHP_QMSPI_DLY_CK_STP_CS_OFF_MASK 0x0f00u 304 #define MCHP_QMSPI_DLY_LST_DAT_HLD_POS 16u 305 #define MCHP_QMSPI_DLY_LST_DAT_HLD_MASK 0x0f0000u 306 #define MCHP_QMSPI_DLY_CS_OFF_CS_ON_POS 24u 307 #define MCHP_QMSPI_DLY_CS_OFF_CS_ON_MASK 0x0f000000u 308 309 /* Alias Control (WO) */ 310 #define MCHP_QMSPI_ACTRL_MASK 0xffffff7fu 311 #define MCHP_QMSPI_ACTRL_ESTART BIT(0) 312 #define MCHP_QMSPI_ACTRL_CDE BIT(1) 313 #define MCHP_QMSPI_ACTRL_TXBW BIT(2) 314 #define MCHP_QMSPI_ACTRL_DLEN BIT(3) 315 #define MCHP_QMSPI_ACTRL_CS_POS 4 316 #define MCHP_QMSPI_ACTRL_CS0 0u 317 #define MCHP_QMSPI_ACTRL_CS1 0x10u 318 #define MCHP_QMSPI_ACTRL_LDIA BIT(6) 319 #define MCHP_QMSPI_ACTRL_DBP_POS 8 320 #define MCHP_QMSPI_ACTRL_DBP_0 0u 321 #define MCHP_QMSPI_ACTRL_DBP_1 0x100u 322 #define MCHP_QMSPI_ACTRL_DBP_N(n) SHLU32(((n) & 0xFu), 8) 323 #define MCHP_QMSPI_ACTRL_BSEL_POS 12 324 #define MCHP_QMSPI_ACTRL_BSEL_MSK 0xf000u 325 #define MCHP_QMSPI_ACTRL_DBLEN_POS 16 326 #define MCHP_QMSPI_ACTRL_DBLEN_MSK 0xff0000u 327 #define MCHP_QMSPI_ACTRL_TXB_DATA_POS 24 328 #define MCHP_QMSPI_ACTRL_TXB_DATA_MSK 0xff000000u 329 330 /* Mode Alternate 1 (RW) */ 331 #define MCHP_QMSPI_MA1_MASK 0xffff0001u 332 #define MCHP_QMSPI_MA1_CS1_CDIV_EN BIT(0) 333 #define MCHP_QMSPI_MA1_CS1_CDIV_POS 16 334 #define MCHP_QMSPI_MA1_CS1_CDIV_MSK 0xffff0000u 335 336 /* TAPS select and TAPS Adjust registers */ 337 #define MCHP_QMSPI_TAPS_MASK 0xffffu 338 #define MCHP_QMSPI_TAPS_SCK_MASK 0xffu 339 #define MCHP_QMSPI_TAPS_CTL_MASK 0xff00u 340 341 /* TAPS Control register */ 342 #define MCHP_QMSPI_TCTRL_MASK 0x70107u 343 #define MCHP_QMSPI_TCTRL_AUTO_MODE_MASK 0x03u 344 #define MCHP_QMSPI_TCTRL_AM_OFF 0x00u 345 #define MCHP_QMSPI_TCTRL_AM_ON 0x01u 346 #define MCHP_QMSPI_TCTRL_AM_PERIODIC 0x02u 347 #define MCHP_QMSPI_TCTRL_UPDATE_EN BIT(2) 348 #define MCHP_QMSPI_TCTRL_UPDATE_NOW BIT(8) 349 #define MCHP_QMSPI_TCTRL_MULT_POS 16 350 #define MCHP_QMSPI_TCTRL_MULT_MSK 0x70000u 351 352 /* Local DMA RX Descriptor Enable bit map */ 353 /* Local DMA TX Descriptor Enable bit map */ 354 #define MCHP_QMSPI_LDMA_DESCR_EN_MASK 0xffffu 355 #define MCHP_QMSPI_LDMA_DESCR_EN(n) BIT((n) & 0xfu) 356 357 /* Each Local DMA channel implements 4 32-bit registers. 358 * Channels are identical for RX and TX 359 * offset 0x00: Control 360 * offset 0x04: memory start address 361 * offset 0x08: transfer byte length 362 * offset 0x0c: reserved read-only 0 363 */ 364 365 /* LDMA Channel Control register */ 366 #define MCHP_QMSPI_LDC_MASK 0x7fu 367 /* enable channel */ 368 #define MCHP_QMSPI_LDC_EN BIT(0) 369 /* re-enable channel upon done */ 370 #define MCHP_QMSPI_LDC_RS_EN BIT(1) 371 /* on restart put memory start address back to its original value */ 372 #define MCHP_QMSPI_LDC_RSA_EN BIT(2) 373 /* use channel length not length in descriptor */ 374 #define MCHP_QMSPI_LDC_UCHL_EN BIT(3) 375 /* LDMA unit(access) size: 1, 2, or 4 bytes */ 376 #define MCHP_QMSPI_LDC_ASZ_POS 4 377 #define MCHP_QMSPI_LDC_ASZ_MSK 0x30u 378 #define MCHP_QMSPI_LDC_ASZ_1 0u 379 #define MCHP_QMSPI_LDC_ASZ_2 0x10u 380 #define MCHP_QMSPI_LDC_ASZ_4 0x20u 381 /* LDMA increment memory start address by access size */ 382 #define MCHP_QMSPI_LDC_INCR_EN BIT(6) 383 384 /* LDMA Channel (memory) Start address register */ 385 #define MCHP_QMSPI_LDMS_MASK 0xffffffffu 386 387 /* LDMA Channel Length register */ 388 #define MCHP_QMSPI_LDLEN_MASK 0xffffffffu 389 390 /** @brief QMSPI Local DMA channel registers */ 391 struct qldma_chan { 392 volatile uint32_t CTRL; 393 volatile uint32_t MSTART; 394 volatile uint32_t LEN; 395 uint32_t RSVD1[1]; 396 }; 397 398 /** @brief QMSPI controller. Size = 368(0x170) */ 399 struct qmspi_regs { 400 volatile uint32_t MODE; 401 volatile uint32_t CTRL; 402 volatile uint32_t EXE; 403 volatile uint32_t IFCTRL; 404 volatile uint32_t STS; 405 volatile uint32_t BCNT_STS; 406 volatile uint32_t IEN; 407 volatile uint32_t BCNT_TRIG; 408 volatile uint32_t TX_FIFO; 409 volatile uint32_t RX_FIFO; 410 volatile uint32_t CSTM; 411 uint32_t RSVD1[1]; 412 volatile uint32_t DESCR[16]; 413 uint32_t RSVD2[16]; 414 volatile uint32_t ALIAS_CTRL; 415 uint32_t RSVD3[3]; 416 volatile uint32_t MODE_ALT1; 417 uint32_t RSVD4[3]; 418 volatile uint32_t TM_TAPS; 419 volatile uint32_t TM_TAPS_ADJ; 420 volatile uint32_t TM_TAPS_CTRL; 421 uint32_t RSVD5[9]; 422 volatile uint32_t LDMA_RX_DESCR_BM; 423 volatile uint32_t LDMA_TX_DESCR_BM; 424 uint32_t RSVD6[2]; 425 struct qldma_chan LDRX[3]; 426 struct qldma_chan LDTX[3]; 427 }; 428 429 #endif /* #ifndef _MEC_QSPI_H */ 430
