1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_ADC_H 8 #define _MEC_ADC_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Eight ADC channels numbered 0 - 7 */ 14 #define MCHP_ADC_MAX_CHAN 8u 15 #define MCHP_ADC_MAX_CHAN_MASK 0x07u 16 17 /* Control register */ 18 #define MCHP_ADC_CTRL_REG_OFS 0u 19 #define MCHP_ADC_CTRL_REG_MASK 0xdfu 20 #define MCHP_ADC_CTRL_REG_RW_MASK 0x1fu 21 #define MCHP_ADC_CTRL_REG_RW1C_MASK 0xc0u 22 #define MCHP_ADC_CTRL_ACTV BIT(0) 23 #define MCHP_ADC_CTRL_START_SNGL BIT(1) 24 #define MCHP_ADC_CTRL_START_RPT BIT(2) 25 #define MCHP_ADC_CTRL_PWRSV_DIS BIT(3) 26 #define MCHP_ADC_CTRL_SRST BIT(4) 27 #define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */ 28 #define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */ 29 30 /* Delay register. Start and repeat delays in units of 40 us */ 31 #define MCHP_ADC_DELAY_REG_OFS 4u 32 #define MCHP_ADC_DELAY_REG_MASK 0xffffffffu 33 #define MCHP_ADC_DELAY_START_POS 0u 34 #define MCHP_ADC_DELAY_START_MASK 0xffffu 35 #define MCHP_ADC_DELAY_RPT_POS 16u 36 #define MCHP_ADC_DELAY_RPT_MASK 0xffff0000u 37 38 /* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */ 39 #define MCHP_ADC_STATUS_REG_OFS 8u 40 #define MCHP_ADC_STATUS_REG_MASK 0xffffu 41 #define MCHP_ADC_STATUS_CHAN(n) BIT(n) 42 43 /* Single Conversion Select register */ 44 #define MCHP_ADC_SCS_REG_OFS 0x0cu 45 #define MCHP_ADC_SCS_REG_MASK 0xffu 46 #define MCHP_ADC_SCS_CH_0_7 0xffu 47 #define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07u)) 48 49 /* Repeat Conversion Select register */ 50 #define MCHP_ADC_RCS_REG_OFS 0x10u 51 #define MCHP_ADC_RCS_REG_MASK 0xffu 52 #define MCHP_ADC_RCS_CH_0_7 0xffu 53 #define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07u)) 54 55 /* Channel reading registers */ 56 #define MCHP_ADC_RDCH_REG_MASK 0xfffu 57 #define MCHP_ADC_RDCH0_REG_OFS 0x14u 58 #define MCHP_ADC_RDCH1_REG_OFS 0x18u 59 #define MCHP_ADC_RDCH2_REG_OFS 0x1cu 60 #define MCHP_ADC_RDCH3_REG_OFS 0x20u 61 #define MCHP_ADC_RDCH4_REG_OFS 0x24u 62 #define MCHP_ADC_RDCH5_REG_OFS 0x28u 63 #define MCHP_ADC_RDCH6_REG_OFS 0x2cu 64 #define MCHP_ADC_RDCH7_REG_OFS 0x30u 65 66 /* Configuration register */ 67 #define MCHP_ADC_CFG_REG_OFS 0x7cu 68 #define MCHP_ADC_CFG_REG_MASK 0xffffu 69 #define MCHP_ADC_CFG_CLK_LO_TIME_POS 0 70 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu 71 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu 72 #define MCHP_ADC_CFG_CLK_HI_TIME_POS 8 73 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu 74 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK SHLU32(0xffu, 8) 75 76 /* Channel Vref Select register */ 77 #define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u 78 #define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu 79 #define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u)) 80 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u 81 #define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u)) 82 83 /* Vref Control register */ 84 #define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u 85 #define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu 86 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0 87 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu 88 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu 89 #define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16 90 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu 91 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK SHLU32(0x1fffu, 16) 92 #define MCHP_ADC_VREF_CTRL_PAD_POS 29 93 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0u 94 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29) 95 #define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30 96 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u 97 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK SHLU32(3u, 30) 98 99 /* SAR ADC Control register */ 100 #define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u 101 #define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001ff8fu 102 /* Select single ended or differential operation */ 103 #define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0 104 #define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0u 105 #define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0) 106 /* Select resolution */ 107 #define MCHP_ADC_SAR_CTRL_RES_POS 1 108 #define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u 109 #define MCHP_ADC_SAR_CTRL_RES_MASK 0x06u 110 #define MCHP_ADC_SAR_CTRL_RES_10_BITS 0x04u 111 #define MCHP_ADC_SAR_CTRL_RES_12_BITS 0x06u 112 /* Shift data in reading register */ 113 #define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3 114 #define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0u 115 #define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3) 116 /* Warm up delay in ADC clock cycles */ 117 #define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7 118 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3ffu 119 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK SHLU32(0x3ffu, 7) 120 #define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT SHLU32(0x202u, 7) 121 122 /* Register interface */ 123 #define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK) 124 #define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) * 4u) 125 #define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n)) 126 127 /** @brief Analog to Digital Converter Registers (ADC) */ 128 struct adc_regs { 129 volatile uint32_t CONTROL; 130 volatile uint32_t DELAY; 131 volatile uint32_t STATUS; 132 volatile uint32_t SINGLE; 133 volatile uint32_t REPEAT; 134 volatile uint32_t RD[8]; 135 uint8_t RSVD1[0x7c - 0x34]; 136 volatile uint32_t CONFIG; 137 volatile uint32_t VREF_CHAN_SEL; 138 volatile uint32_t VREF_CTRL; 139 volatile uint32_t SARADC_CTRL; 140 }; 141 142 #endif /* #ifndef _MEC_ADC_H */ 143
