1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature 2 * sensor driver 3 */ 4 5 /* 6 * Copyright (c) 2017 Linaro Limited 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_SENSOR_LPS22HB_LPS22HB_H_ 12 #define ZEPHYR_DRIVERS_SENSOR_LPS22HB_LPS22HB_H_ 13 14 #include <stdint.h> 15 #include <drivers/i2c.h> 16 #include <sys/util.h> 17 18 #define LPS22HB_REG_WHO_AM_I 0x0F 19 #define LPS22HB_VAL_WHO_AM_I 0xB1 20 21 #define LPS22HB_REG_INTERRUPT_CFG 0x0B 22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7) 23 #define LPS22HB_SHIFT_INTERRUPT_CFG_AUTORIFP 7 24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6) 25 #define LPS22HB_SHIFT_INTERRUPT_CFG_RESET_ARP 6 26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5) 27 #define LPS22HB_SHIFT_INTERRUPT_CFG_AUTOZERO 5 28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4) 29 #define LPS22HB_SHIFT_INTERRUPT_CFG_RESET_AZ 4 30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3) 31 #define LPS22HB_SHIFT_INTERRUPT_CFG_DIFF_EN 3 32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2) 33 #define LPS22HB_SHIFT_INTERRUPT_CFG_LIR 2 34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1) 35 #define LPS22HB_SHIFT_INTERRUPT_CFG_PL_E 1 36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E BIT(0) 37 #define LPS22HB_SHIFT_INTERRUPT_CFG_PH_E 0 38 39 #define LPS22HB_REG_THS_P_L 0x0C 40 #define LPS22HB_REG_THS_P_H 0x0D 41 42 #define LPS22HB_REG_CTRL_REG1 0x10 43 #define LPS22HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4)) 44 #define LPS22HB_SHIFT_CTRL_REG1_ODR 4 45 #define LPS22HB_MASK_CTRL_REG1_EN_LPFP BIT(3) 46 #define LPS22HB_SHIFT_CTRL_REG1_EN_LPFP 3 47 #define LPS22HB_MASK_CTRL_REG1_LPFP_CFG BIT(2) 48 #define LPS22HB_SHIFT_CTRL_REG1_LPFP_CFG 2 49 #define LPS22HB_MASK_CTRL_REG1_BDU BIT(1) 50 #define LPS22HB_SHIFT_CTRL_REG1_BDU 1 51 #define LPS22HB_MASK_CTRL_REG1_SIM BIT(0) 52 #define LPS22HB_SHIFT_CTRL_REG1_SIM 0 53 54 #define LPS22HB_REG_CTRL_REG2 0x11 55 #define LPS22HB_MASK_CTRL_REG2_BOOT BIT(7) 56 #define LPS22HB_SHIFT_CTRL_REG2_BOOT 7 57 #define LPS22HB_MASK_CTRL_REG2_FIFO_EN BIT(6) 58 #define LPS22HB_SHIFT_CTRL_REG2_FIFO_EN 6 59 #define LPS22HB_MASK_CTRL_REG2_STOP_ON_FTH BIT(5) 60 #define LPS22HB_SHIFT_CTRL_REG2_STOP_ON_FTH 5 61 #define LPS22HB_MASK_CTRL_REG2_IF_ADD_INC BIT(4) 62 #define LPS22HB_SHIFT_CTRL_REG2_IF_ADD_INC 4 63 #define LPS22HB_MASK_CTRL_REG2_I2C_DIS BIT(3) 64 #define LPS22HB_SHIFT_CTRL_REG2_I2C_DIS 3 65 #define LPS22HB_MASK_CTRL_REG2_SWRESET BIT(2) 66 #define LPS22HB_SHIFT_CTRL_REG2_SWRESET 2 67 #define LPS22HB_MASK_CTRL_REG2_ONE_SHOT BIT(0) 68 #define LPS22HB_SHIFT_CTRL_REG2_ONE_SHOT 0 69 70 #define LPS22HB_REG_CTRL_REG3 0x12 71 #define LPS22HB_MASK_CTRL_REG3_INT_H_L BIT(7) 72 #define LPS22HB_SHIFT_CTRL_REG3_INT_H_L 7 73 #define LPS22HB_MASK_CTRL_REG3_PP_OD BIT(6) 74 #define LPS22HB_SHIFT_CTRL_REG3_PP_OD 6 75 #define LPS22HB_MASK_CTRL_REG3_F_FSS5 BIT(5) 76 #define LPS22HB_SHIFT_CTRL_REG3_F_FFS5 5 77 #define LPS22HB_MASK_CTRL_REG3_F_FTH BIT(4) 78 #define LPS22HB_SHIFT_CTRL_REG3_F_FTH 4 79 #define LPS22HB_MASK_CTRL_REG3_F_OVR BIT(3) 80 #define LPS22HB_SHIFT_CTRL_REG3_F_OVR 3 81 #define LPS22HB_MASK_CTRL_REG3_DRDY BIT(2) 82 #define LPS22HB_SHIFT_CTRL_REG3_DRDY 2 83 #define LPS22HB_MASK_CTRL_REG3_INT_S (BIT(1) | BIT(0)) 84 #define LPS22HB_SHIFT_CTRL_REG_INT_S 0 85 86 #define LPS22HB_REG_FIFO_CTRL 0x14 87 #define LPS22HB_MASK_FIFO_CTRL_F_MODE (BIT(7) | BIT(6) | BIT(5)) 88 #define LPS22HB_SHIFT_FIFO_CTRL_F_MODE 5 89 #define LPS22HB_MASK_FIFO_CTRL_WTM (BIT(4) | BIT(3) | BIT(2) | \ 90 BIT(2) | BIT(1) | BIT(0)) 91 #define LPS22HB_SHIFT_FIFO_CTRL_WTM 0 92 93 #define LPS22HB_REG_REF_P_XL 0x15 94 #define LPS22HB_REG_REF_P_L 0x16 95 #define LPS22HB_REG_REF_P_H 0x17 96 97 #define LPS22HB_REG_RPDS_L 0x18 98 #define LPS22HB_REG_RPDS_H 0x19 99 100 #define LPS22HB_REG_RES_CONF 0x1A 101 #define LPS22HB_MASK_RES_CONF_LC_EN BIT(0) 102 #define LPS22HB_SHIFT_RES_CONF_LC_EN 0 103 104 #define LPS22HB_REG_INT_SOURCE 0x25 105 #define LPS22HB_MASK_INT_SOURCE_IA BIT(2) 106 #define LPS22HB_SHIFT_INT_SOURCE_IA 2 107 #define LPS22HB_MASK_INT_SOURCE_PL BIT(1) 108 #define LPS22HB_SHIFT_INT_SOURCE_PL 1 109 #define LPS22HB_MASK_INT_SOURCE_PH BIT(0) 110 #define LPS22HB_SHIFT_INT_SOURCE_PH 0 111 112 #define LPS22HB_REG_FIFO_STATUS 0x26 113 #define LPS22HB_MASK_FIFO_STATUS_FTH_FIFO BIT(7) 114 #define LPS22HB_SHIFT_FIFO_STATUS_FTH_FIFO 7 115 #define LPS22HB_MASK_FIFO_STATUS_OVR BIT(6) 116 #define LPS22HB_SHIFT_FIFO_STATUS_OVR 6 117 #define LPS22HB_MASK_FIFO_STATUS_EMPTY_FIFO BIT(5) 118 #define LPS22HB_SHIFT_FIFO_STATUS_EMPTY_FIFO 5 119 #define LPS22HB_MASK_FIFO_STATUS_FSS (BIT(4) | BIT(3) | BIT(2) | \ 120 BIT(1) | BIT(0)) 121 #define LPS22HB_SHIFT_FIFO_STATUS_FSS 0 122 123 #define LPS22HB_REG_STATUS 0x27 124 #define LPS22HB_MASK_STATUS_P_OR BIT(5) 125 #define LPS22HB_SHIFT_STATUS_P_OR 5 126 #define LPS22HB_MASK_STATUS_T_OR BIT(4) 127 #define LPS22HB_SHIFT_STATUS_T_OR 4 128 #define LPS22HB_MASK_STATUS_P_DA BIT(1) 129 #define LPS22HB_SHIFT_STATUS_P_DA 1 130 #define LPS22HB_MASK_STATUS_T_DA BIT(0) 131 #define LPS22HB_SHIFT_STATUS_T_DA 0 132 133 #define LPS22HB_REG_PRESS_OUT_XL 0x28 134 #define LPS22HB_REG_PRESS_OUT_L 0x29 135 #define LPS22HB_REG_PRESS_OUT_H 0x2A 136 137 #define LPS22HB_REG_TEMP_OUT_L 0x2B 138 #define LPS22HB_REG_TEMP_OUT_H 0x2C 139 140 #define LPS22HB_REG_LPFP_RES 0x33 141 142 143 #if CONFIG_LPS22HB_SAMPLING_RATE == 1 144 #define LPS22HB_DEFAULT_SAMPLING_RATE 1 145 #elif CONFIG_LPS22HB_SAMPLING_RATE == 10 146 #define LPS22HB_DEFAULT_SAMPLING_RATE 2 147 #elif CONFIG_LPS22HB_SAMPLING_RATE == 25 148 #define LPS22HB_DEFAULT_SAMPLING_RATE 3 149 #elif CONFIG_LPS22HB_SAMPLING_RATE == 50 150 #define LPS22HB_DEFAULT_SAMPLING_RATE 4 151 #elif CONFIG_LPS22HB_SAMPLING_RATE == 75 152 #define LPS22HB_DEFAULT_SAMPLING_RATE 5 153 #endif 154 155 156 struct lps22hb_config { 157 char *i2c_master_dev_name; 158 uint16_t i2c_slave_addr; 159 }; 160 161 struct lps22hb_data { 162 const struct device *i2c_master; 163 int32_t sample_press; 164 int16_t sample_temp; 165 }; 166 167 #endif /* ZEPHYR_DRIVERS_SENSOR_LPS22HB_LPS22HB_H_ */ 168
