1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_ESPI_IO_H 8 #define _MEC172X_ESPI_IO_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Offsets from base for various register groups */ 14 #define MCHP_ESPI_IO_PC_OFS 0x0100u 15 #define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120u 16 #define MCHP_ESPI_IO_LTR_OFS 0x0220u 17 #define MCHP_ESPI_IO_OOB_OFS 0x0240u 18 #define MCHP_ESPI_IO_FC_OFS 0x0280u 19 #define MCHP_ESPI_IO_CAP_OFS 0x02b0u 20 #define MCHP_ESPI_IO_SIRQ_OFS 0x03a0u 21 22 /* eSPI Global Capabilities 0 */ 23 #define MCHP_ESPI_GBL_CAP0_MASK 0x0fu 24 #define MCHP_ESPI_GBL_CAP0_PC_SUPP BIT(0) 25 #define MCHP_ESPI_GBL_CAP0_VW_SUPP BIT(1) 26 #define MCHP_ESPI_GBL_CAP0_OOB_SUPP BIT(2) 27 #define MCHP_ESPI_GBL_CAP0_FC_SUPP BIT(3) 28 29 /* eSPI Global Capabilities 1 */ 30 #define MCHP_ESPI_GBL_CAP1_MASK 0xffu 31 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u 32 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u 33 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u 34 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u 35 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u 36 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u 37 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u 38 #define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */ 39 #define MCHP_ESPI_GBL_CAP1_ALERT_DED_PIN \ 40 BIT(MCHP_ESPI_GBL_CAP1_ALERT_POS) 41 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u 42 #define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4u 43 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u 44 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK SHLU32(0x03u, 4) 45 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u 46 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u 47 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u 48 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u 49 #define MCHP_ESPI_GBL_CAP1_IO_MODE_1 \ 50 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_1, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) 51 52 #define MCHP_ESPI_GBL_CAP1_IO_MODE_12 \ 53 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_12, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) 54 55 #define MCHP_ESPI_GBL_CAP1_IO_MODE_14 \ 56 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_14, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) 57 58 #define MCHP_ESPI_GBL_CAP1_IO_MODE_124 \ 59 SHLU32(MCHP_ESPI_GBL_CAP1_IO_MODE0_124, MCHP_ESPI_GBL_CAP1_IO_MODE_POS) 60 61 /* 62 * Support Open Drain ALERT pin configuration 63 * EC sets this bit if it can support open-drain ESPI_ALERT# 64 */ 65 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS 6u 66 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS) 67 68 /* 69 * Read-Only ALERT Open Drain select. 70 * If EC has indicated it can support open-drain ESPI_ALERT# then 71 * the Host can enable open-drain ESPI_ALERT# by sending a configuraiton 72 * message. This read-only bit relects the configuration selection. 73 */ 74 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS 7u 75 #define MCHP_ESPI_GBL_CAP1_ALERT_SEL_ODS \ 76 BIT(MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS) 77 78 /* Peripheral Channel(PC) Capabilities */ 79 #define MCHP_ESPI_PC_CAP_MASK 0x07u 80 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u 81 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u 82 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u 83 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u 84 85 /* Virtual Wire(VW) Capabilities */ 86 #define MCHP_ESPI_VW_CAP_MASK 0x3fu 87 #define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3fu 88 89 /* Out-of-Band(OOB) Capabilities */ 90 #define MCHP_ESPI_OOB_CAP_MASK 0x07u 91 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u 92 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u 93 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u 94 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u 95 96 /* Flash Channel(FC) Capabilities */ 97 #define MCHP_ESPI_FC_CAP_MASK 0xffu 98 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u 99 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u 100 #define MCHP_ESPI_FC_CAP_SHARE_POS 3u 101 #define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u 102 #define MCHP_ESPI_FC_CAP_SHARE_MASK \ 103 SHLU32(MCHP_ESPI_FC_CAP_SHARE_MASK0, MCHP_ESPI_FC_CAP_SHARE_POS) 104 105 #define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0u 106 #define MCHP_ESPI_FC_CAP_SHARE_MAF2_ONLY \ 107 SHLU32(1U, MCHP_ESPI_FC_CAP_SHARE_POS) 108 109 #define MCHP_ESPI_FC_CAP_SHARE_SAF_ONLY \ 110 SHLU32(2U, MCHP_ESPI_FC_CAP_SHARE_POS) 111 112 #define MCHP_ESPI_FC_CAP_SHARE_MAF_SAF \ 113 SHLU32(3U, MCHP_ESPI_FC_CAP_SHARE_POS) 114 115 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS 5u 116 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u 117 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK \ 118 SHLU32(MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0, \ 119 MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS) 120 121 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_64 \ 122 BIT(MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS) 123 124 /* PC Ready */ 125 #define MCHP_ESPI_PC_READY_MASK 0x01u; 126 #define MCHP_ESPI_PC_READY 0x01u; 127 128 /* OOB Ready */ 129 #define MCHP_ESPI_OOB_READY_MASK 0x01u; 130 #define MCHP_ESPI_OOB_READY 0x01u; 131 132 /* FC Ready */ 133 #define MCHP_ESPI_FC_READY_MASK 0x01u; 134 #define MCHP_ESPI_FC_READY 0x01u; 135 136 /* ESPI_RESET# Interrupt Status */ 137 #define MCHP_ESPI_RST_ISTS_MASK 0x03u; 138 #define MCHP_ESPI_RST_ISTS_POS 0u 139 #define MCHP_ESPI_RST_ISTS BIT(MCHP_ESPI_RST_ISTS_POS) 140 #define MCHP_ESPI_RST_ISTS_PIN_RO_POS 1u 141 #define MCHP_ESPI_RST_ISTS_PIN_RO_HI BIT(MCHP_ESPI_RST_ISTS_PIN_RO_POS) 142 143 /* ESPI_RESET# Interrupt Enable */ 144 #define MCHP_ESPI_RST_IEN_MASK 0x01u 145 #define MCHP_ESPI_RST_IEN 0x01u 146 147 /* eSPI Platform Reset Source */ 148 #define MCHP_ESPI_PLTRST_SRC_MASK 0x01u 149 #define MCHP_ESPI_PLTRST_SRC_POS 0u 150 #define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01u 151 #define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00u 152 153 /* VW Ready */ 154 #define MCHP_ESPI_VW_READY_MASK 0x01u 155 #define MCHP_ESPI_VW_READY 0x01u 156 157 /* SAF Erase Block size */ 158 #define MCHP_ESPI_SERASE_SZ_1K_BITPOS 0 159 #define MCHP_ESPI_SERASE_SZ_2K_BITPOS 1 160 #define MCHP_ESPI_SERASE_SZ_4K_BITPOS 2 161 #define MCHP_ESPI_SERASE_SZ_8K_BITPOS 3 162 #define MCHP_ESPI_SERASE_SZ_16K_BITPOS 4 163 #define MCHP_ESPI_SERASE_SZ_32K_BITPOS 5 164 #define MCHP_ESPI_SERASE_SZ_64K_BITPOS 6 165 #define MCHP_ESPI_SERASE_SZ_128K_BITPOS 7 166 #define MCHP_ESPI_SERASE_SZ_1K BIT(0) 167 #define MCHP_ESPI_SERASE_SZ_2K BIT(1) 168 #define MCHP_ESPI_SERASE_SZ_4K BIT(2) 169 #define MCHP_ESPI_SERASE_SZ_8K BIT(3) 170 #define MCHP_ESPI_SERASE_SZ_16K BIT(4) 171 #define MCHP_ESPI_SERASE_SZ_32K BIT(5) 172 #define MCHP_ESPI_SERASE_SZ_64K BIT(6) 173 #define MCHP_ESPI_SERASE_SZ_128K BIT(7) 174 #define MCHP_ESPI_SERASE_SZ(bitpos) BIT((bitpos) + 10u) 175 176 /* VW Error Status */ 177 #define MCHP_ESPI_VW_ERR_STS_MASK 0x33u 178 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u 179 #define MCHP_ESPI_VW_ERR_STS_FATAL_RO \ 180 BIT(MCHP_ESPI_VW_ERR_STS_FATAL_POS) 181 182 #define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS 1u 183 #define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_WO \ 184 BIT(MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS) 185 186 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS 4u 187 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_RO \ 188 BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS) 189 190 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS 5u 191 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_WO \ 192 BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS) 193 194 /* VW Channel Enable Status */ 195 #define MCHP_ESPI_VW_EN_STS_MASK 0x01u 196 #define MCHP_ESPI_VW_EN_STS_RO 0x01u 197 198 /* 199 * MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500 200 */ 201 202 /* Peripheral Channel Last Cycle length, type, and tag. */ 203 #define MCHP_ESPI_PC_LC_LEN_POS 0u 204 #define MCHP_ESPI_PC_LC_LEN_MASK0 0x0fffu 205 #define MCHP_ESPI_PC_LC_LEN_MASK 0x0fffu 206 #define MCHP_ESPI_PC_LC_TYPE_POS 12u 207 #define MCHP_ESPI_PC_LC_TYPE_MASK0 0xffu 208 #define MCHP_ESPI_PC_LC_TYPE_MASK (0xffu << 12) 209 #define MCHP_ESPI_PC_LC_TAG_POS 20u 210 #define MCHP_ESPI_PC_LC_TAG_MASK0 0x0fu 211 #define MCHP_ESPI_PC_LC_TAG_MASK (0x0fu << 20) 212 213 /* 214 * Peripheral Channel Status 215 * Bus error, Channel enable change, and Bus master enable change. 216 */ 217 #define MCHP_ESPI_PC_STS_BUS_ERR_POS 16u /* RW1C */ 218 #define MCHP_ESPI_PC_STS_BUS_ERR BIT(MCHP_ESPI_PC_STS_BUS_ERR_POS) 219 #define MCHP_ESPI_PC_STS_EN_POS 24u /* RO */ 220 #define MCHP_ESPI_PC_STS_EN BIT(MCHP_ESPI_PC_STS_EN_POS) 221 #define MCHP_ESPI_PC_STS_EN_CHG_POS 25u /* RW1C */ 222 #define MCHP_ESPI_PC_STS_EN_CHG BIT(MCHP_ESPI_PC_STS_EN_CHG_POS) 223 #define MCHP_ESPI_PC_STS_BM_EN_POS 27u /* RO */ 224 #define MCHP_ESPI_PC_STS_BM_EN BIT(MCHP_ESPI_PC_STS_BM_EN_POS) 225 #define MCHP_ESPI_PC_STS_BM_EN_CHG_POS 28u /* RW1C */ 226 #define MCHP_ESPI_PC_STS_BM_EN_CHG BIT(MCHP_ESPI_PC_STS_BM_EN_CHG_POS) 227 228 /* 229 * Peripheral Channel Interrupt Enables for 230 * Bus error, Channel enable change, and Bus master enable change. 231 * PC_LC_ADDR_LSW (@ 0x0000) Periph Chan Last Cycle address LSW 232 * PC_LC_ADDR_MSW (@ 0x0004) Periph Chan Last Cycle address MSW 233 * PC_LC_LEN_TYPE_TAG (@ 0x0008) Periph Chan Last Cycle length/type/tag 234 * PC_ERR_ADDR_LSW (@ 0x000C) Periph Chan Error Address LSW 235 * PC_ERR_ADDR_MSW (@ 0x0010) Periph Chan Error Address MSW 236 * PC_STATUS (@ 0x0014) Periph Chan Status 237 * PC_IEN (@ 0x0018) Periph Chan IEN 238 */ 239 #define MCHP_ESPI_PC_IEN_BUS_ERR_POS 16u 240 #define MCHP_ESPI_PC_IEN_BUS_ERR BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) 241 #define MCHP_ESPI_PC_IEN_EN_CHG_POS 25u 242 #define MCHP_ESPI_PC_IEN_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) 243 #define MCHP_ESPI_PC_IEN_BM_EN_CHG_POS 28u 244 #define MCHP_ESPI_PC_IEN_BM_EN_CHG BIT(MCHP_ESPI_PC_IEN_BUS_ERR_POS) 245 246 /*---- ESPI_IO_LTR - eSPI IO LTR registers ----*/ 247 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u /* RW1C */ 248 #define MCHP_ESPI_LTR_STS_TX_DONE BIT(MCHP_ESPI_LTR_STS_TX_DONE_POS) 249 #define MCHP_ESPI_LTR_STS_OVRUN_POS 3u /* RW1C */ 250 #define MCHP_ESPI_LTR_STS_OVRUN BIT(MCHP_ESPI_LTR_STS_OVRUN_POS) 251 #define MCHP_ESPI_LTR_STS_HDIS_POS 4u /* RW1C */ 252 #define MCHP_ESPI_LTR_STS_HDIS BIT(MCHP_ESPI_LTR_STS_HDIS_POS) 253 #define MCHP_ESPI_LTR_STS_TX_BUSY_POS 8u /* RO */ 254 #define MCHP_ESPI_LTR_STS_TX_BUSY BIT(MCHP_ESPI_LTR_STS_TX_BUSY_POS) 255 256 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u 257 #define MCHP_ESPI_LTR_IEN_TX_DONE BIT(MCHP_ESPI_LTR_IEN_TX_DONE_POS) 258 259 #define MCHP_ESPI_LTR_CTRL_START_POS 0u 260 #define MCHP_ESPI_LTR_CTRL_START BIT(MCHP_ESPI_LTR_CTRL_START_POS) 261 #define MCHP_ESPI_LTR_CTRL_TAG_POS 8u 262 #define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0fu 263 #define MCHP_ESPI_LTR_CTRL_TAG_MASK \ 264 SHLU32(MCHP_ESPI_LTR_CTRL_TAG_MASK0, MCHP_ESPI_LTR_CTRL_TAG_POS) 265 266 #define MCHP_ESPI_LTR_MSG_VAL_POS 0u 267 #define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3ffu 268 #define MCHP_ESPI_LTR_MSG_VAL_MASK \ 269 SHLU32(MCHP_ESPI_LTR_MSG_VAL_MASK0, MCHP_ESPI_LTR_MSG_VAL_POS) 270 #define MCHP_ESPI_LTR_MSG_SC_POS 10u 271 #define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07u 272 #define MCHP_ESPI_LTR_MSG_SC_MASK \ 273 SHLU32(MCHP_ESPI_LTR_MSG_SC_MASK0, MCHP_ESPI_LTR_MSG_SC_POS) 274 #define MCHP_ESPI_LTR_MSG_RT_POS 13u 275 #define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03u 276 #define MCHP_ESPI_LTR_MSG_RT_MASK \ 277 SHLU32(MCHP_ESPI_LTR_MSG_RT_MASK0, MCHP_ESPI_LTR_MSG_RT_POS) 278 /* eSPI specification indicates RT field must be 00b */ 279 #define MCHP_ESPI_LTR_MSG_RT_VAL 0u 280 #define MCHP_ESPI_LTR_MSG_REQ_POS 15u 281 /* inifinite latency(default) */ 282 #define MCHP_ESPI_LTR_MSG_REQ_INF 0u 283 /* latency computed from VAL and SC(scale) fields */ 284 #define MCHP_ESPI_LTR_MSG_REQ_VAL BIT(MCHP_ESPI_LTR_MSG_REQ_POS) 285 286 /*---- ESPI_IO_OOB - eSPI IO OOB registers ----*/ 287 #define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xfffffffcu 288 #define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xfffffffcu 289 290 /* OOB RX_LEN register */ 291 /* Number of bytes received (RO) */ 292 #define MCHP_ESPI_OOB_RX_LEN_POS 0u 293 #define MCHP_ESPI_OOB_RX_LEN_MASK 0x1fffu 294 /* Receive buffer length field (RW) */ 295 #define MCHP_ESPI_OOB_RX_BUF_LEN_POS 16u 296 #define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x1fffu 297 #define MCHP_ESPI_OOB_RX_BUF_LEN_MASK \ 298 SHLU32(MCHP_ESPI_OOB_RX_BUF_LEN_MASK0, MCHP_ESPI_OOB_RX_BUF_LEN_POS) 299 300 /* OOB TX_LEN register */ 301 #define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u 302 #define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x1fffu 303 304 /* OOB RX_CTRL */ 305 /* Set AVAIL bit to indicate SRAM Buffer and size has been configured */ 306 #define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u /* WO */ 307 #define MCHP_ESPI_OOB_RX_CTRL_AVAIL BIT(MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS) 308 #define MCHP_ESPI_OOB_RX_CTRL_CHEN_POS 9u /* RO */ 309 #define MCHP_ESPI_OOB_RX_CTRL_CHEN BIT(MCHP_ESPI_OOB_RX_CTRL_CHEN_POS) 310 /* Copy of eSPI OOB Capabilities max. payload size */ 311 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS 16u /* RO */ 312 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u 313 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK \ 314 SHLU32(MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0, \ 315 MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS) 316 317 /* OOB RX_IEN */ 318 #define MCHP_ESPI_OOB_RX_IEN_POS 0u 319 #define MCHP_ESPI_OOB_RX_IEN BIT(MCHP_ESPI_OOB_RX_IEN_POS) 320 321 /* OOB RX_STS */ 322 #define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u /* RW1C */ 323 #define MCHP_ESPI_OOB_RX_STS_DONE BIT(MCHP_ESPI_OOB_RX_STS_DONE_POS) 324 #define MCHP_ESPI_OOB_RX_STS_IBERR_POS 1u /* RW1C */ 325 #define MCHP_ESPI_OOB_RX_STS_IBERR BIT(MCHP_ESPI_OOB_RX_STS_IBERR_POS) 326 #define MCHP_ESPI_OOB_RX_STS_OVRUN_POS 2u /* RW1C */ 327 #define MCHP_ESPI_OOB_RX_STS_OVRUN BIT(MCHP_ESPI_OOB_RX_STS_OVRUN_POS) 328 #define MCHP_ESPI_OOB_RX_STS_RXEN_POS 3u /* RO */ 329 #define MCHP_ESPI_OOB_RX_STS_RXEN BIT(MCHP_ESPI_OOB_RX_STS_RXEN_POS) 330 #define MCHP_ESPI_OOB_RX_STS_TAG_POS 8u /* RO */ 331 #define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0fu 332 #define MCHP_ESPI_OOB_RX_STS_TAG_MASK \ 333 SHLU32(MCHP_ESPI_OOB_RX_STS_TAG_MASK0, MCHP_ESPI_OOB_RX_STS_TAG_POS) 334 335 #define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x07u 336 #define MCHP_ESPI_OOB_RX_STS_ALL 0x0fu 337 338 /* OOB TX_CTRL */ 339 #define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u /* WO */ 340 #define MCHP_ESPI_OOB_TX_CTRL_START BIT(MCHP_ESPI_OOB_TX_CTRL_START_POS) 341 #define MCHP_ESPI_OOB_TX_CTRL_TAG_POS 8u /* RW */ 342 #define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0fu 343 #define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK \ 344 SHLU32(MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0, MCHP_ESPI_OOB_TX_CTRL_TAG_POS) 345 346 /* OOB TX_IEN */ 347 #define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u 348 #define MCHP_ESPI_OOB_TX_IEN_DONE BIT(MCHP_ESPI_OOB_TX_IEN_DONE_POS) 349 #define MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS 1u 350 #define MCHP_ESPI_OOB_TX_IEN_CHG_EN BIT(MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS) 351 #define MCHP_ESPI_OOB_TX_IEN_ALL 0x03u 352 353 /* OOB TX_STS */ 354 #define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u /* RW1C */ 355 #define MCHP_ESPI_OOB_TX_STS_DONE BIT(MCHP_ESPI_OOB_TX_STS_DONE_POS) 356 #define MCHP_ESPI_OOB_TX_STS_CHG_EN_POS 1u /* RW1C */ 357 #define MCHP_ESPI_OOB_TX_STS_CHG_EN BIT(MCHP_ESPI_OOB_TX_STS_CHG_EN_POS) 358 #define MCHP_ESPI_OOB_TX_STS_IBERR_POS 2u /* RW1C */ 359 #define MCHP_ESPI_OOB_TX_STS_IBERR BIT(MCHP_ESPI_OOB_TX_STS_IBERR_POS) 360 #define MCHP_ESPI_OOB_TX_STS_OVRUN_POS 3u /* RW1C */ 361 #define MCHP_ESPI_OOB_TX_STS_OVRUN BIT(MCHP_ESPI_OOB_TX_STS_OVRUN_POS) 362 #define MCHP_ESPI_OOB_TX_STS_BADREQ_POS 5u /* RW1C */ 363 #define MCHP_ESPI_OOB_TX_STS_BADREQ BIT(MCHP_ESPI_OOB_TX_STS_BADREQ_POS) 364 #define MCHP_ESPI_OOB_TX_STS_BUSY_POS 8u /* RO */ 365 #define MCHP_ESPI_OOB_TX_STS_BUSY BIT(MCHP_ESPI_OOB_TX_STS_BUSY_POS) 366 /* Read-only copy of OOB Channel Enabled bit */ 367 #define MCHP_ESPI_OOB_TX_STS_CHEN_POS 9u /* RO */ 368 #define MCHP_ESPI_OOB_TX_STS_CHEN BIT(MCHP_ESPI_OOB_TX_STS_CHEN_POS) 369 370 #define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2fu 371 372 /*---- MCHP_ESPI_IO_FC - eSPI IO Flash channel registers ----*/ 373 /* FC MEM_ADDR_LSW */ 374 #define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xfffffffcu 375 376 /* FC CTRL */ 377 #define MCHP_ESPI_FC_CTRL_START_POS 0u /* WO */ 378 #define MCHP_ESPI_FC_CTRL_START BIT(MCHP_ESPI_FC_CTRL_START_POS) 379 #define MCHP_ESPI_FC_CTRL_FUNC_POS 2u /* RW */ 380 #define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03u 381 #define MCHP_ESPI_FC_CTRL_FUNC_MASK \ 382 SHLU32(MCHP_ESPI_FC_CTRL_FUNC_MASK0, MCHP_ESPI_FC_CTRL_FUNC_POS) 383 #define MCHP_ESPI_FC_CTRL_RD0 0x00u 384 #define MCHP_ESPI_FC_CTRL_WR0 0x01u 385 #define MCHP_ESPI_FC_CTRL_ERS0 0x02u 386 #define MCHP_ESPI_FC_CTRL_ERL0 0x03u 387 #define MCHP_ESPI_FC_CTRL_FUNC(f) \ 388 ((uint32_t)(f) & MCHP_ESPI_FC_CTRL_FUNC_MASK) 389 390 #define MCHP_ESPI_FC_CTRL_TAG_POS 4u 391 #define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0fu 392 #define MCHP_ESPI_FC_CTRL_TAG_MASK \ 393 SHLU32(MCHP_ESPI_FC_CTRL_TAG_MASK0, MCHP_ESPI_FC_CTRL_TAG_POS) 394 395 #define MCHP_ESPI_FC_CTRL_TAG(t) \ 396 ((uint32_t)(t) & MCHP_ESPI_FC_CTRL_TAG_MASK) 397 398 #define MCHP_ESPI_FC_CTRL_ABORT_POS 16u /* WO */ 399 #define MCHP_ESPI_FC_CTRL_ABORT BIT(MCHP_ESPI_FC_CTRL_ABORT_POS) 400 401 /* FC IEN */ 402 #define MCHP_ESPI_FC_IEN_DONE_POS 0u 403 #define MCHP_ESPI_FC_IEN_DONE BIT(MCHP_ESPI_FC_IEN_DONE_POS) 404 #define MCHP_ESPI_FC_IEN_CHG_EN_POS 1u 405 #define MCHP_ESPI_FC_IEN_CHG_EN BIT(MCHP_ESPI_FC_IEN_CHG_EN_POS) 406 407 /* FC CFG */ 408 #define MCHP_ESPI_FC_CFG_BUSY_POS 0u /* RO */ 409 #define MCHP_ESPI_FC_CFG_BUSY BIT(MCHP_ESPI_FC_CFG_BUSY_POS) 410 #define MCHP_ESPI_FC_CFG_ERBSZ_POS 2u /* RO */ 411 #define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07u 412 #define MCHP_ESPI_FC_CFG_ERBSZ_MASK \ 413 SHLU32(MCHP_ESPI_FC_CFG_ERBSZ_MASK0, MCHP_ESPI_FC_CFG_ERBSZ_POS) 414 #define MCHP_ESPI_FC_CFG_ERBSZ_4K \ 415 SHLU32(0x01u, MCHP_ESPI_FC_CFG_ERBSZ_POS) 416 #define MCHP_ESPI_FC_CFG_ERBSZ_64K \ 417 SHLU32(0x02u, MCHP_ESPI_FC_CFG_ERBSZ_POS) 418 #define MCHP_ESPI_FC_CFG_ERBSZ_4K_64K \ 419 SHLU32(0x03u, MCHP_ESPI_FC_CFG_ERBSZ_POS) 420 #define MCHP_ESPI_FC_CFG_ERBSZ_128K \ 421 SHLU32(0x04u, MCHP_ESPI_FC_CFG_ERBSZ_POS) 422 #define MCHP_ESPI_FC_CFG_ERBSZ_256K \ 423 SHLU32(0x05u, MCHP_ESPI_FC_CFG_ERBSZ_POS) 424 #define MCHP_ESPI_FC_CFG_MAXPLD_POS 8u /* RO */ 425 #define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07u 426 #define MCHP_ESPI_FC_CFG_MAXPLD_MASK \ 427 SHLU32(MCHP_ESPI_FC_CFG_MAXPLD_MASK0, MCHP_ESPI_FC_CFG_MAXPLD_POS) 428 #define MCHP_ESPI_FC_CFG_MAXPLD_64B \ 429 SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXPLD_POS) 430 #define MCHP_ESPI_FC_CFG_MAXPLD_128B \ 431 SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXPLD_POS) 432 #define MCHP_ESPI_FC_CFG_MAXPLD_256B \ 433 SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXPLD_POS) 434 #define MCHP_ESPI_FC_CFG_SAFS_SEL_POS 11u 435 #define MCHP_ESPI_FC_CFG_SAFS_SEL BIT(MCHP_ESPI_FC_CFG_SAFS_SEL_POS) 436 #define MCHP_ESPI_FC_CFG_MAXRD_POS 12u /* RO */ 437 #define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07u 438 #define MCHP_ESPI_FC_CFG_MAXRD_MASK \ 439 SHLU32(MCHP_ESPI_FC_CFG_MAXRD_MASK0, MCHP_ESPI_FC_CFG_MAXRD_POS) 440 #define MCHP_ESPI_FC_CFG_MAXRD_64B \ 441 SHLU32(0x01u, MCHP_ESPI_FC_CFG_MAXRD_POS) 442 #define MCHP_ESPI_FC_CFG_MAXRD_128B \ 443 SHLU32(0x02u, MCHP_ESPI_FC_CFG_MAXRD_POS) 444 #define MCHP_ESPI_FC_CFG_MAXRD_256B \ 445 SHLU32(0x03u, MCHP_ESPI_FC_CFG_MAXRD_POS) 446 #define MCHP_ESPI_FC_CFG_MAXRD_512B \ 447 SHLU32(0x04u, MCHP_ESPI_FC_CFG_MAXRD_POS) 448 #define MCHP_ESPI_FC_CFG_MAXRD_1K \ 449 SHLU32(0x05u, MCHP_ESPI_FC_CFG_MAXRD_POS) 450 #define MCHP_ESPI_FC_CFG_MAXRD_2K \ 451 SHLU32(0x06u, MCHP_ESPI_FC_CFG_MAXRD_POS) 452 #define MCHP_ESPI_FC_CFG_MAXRD_4K \ 453 SHLU32(0x07u, MCHP_ESPI_FC_CFG_MAXRD_POS) 454 #define MCHP_ESPI_FC_CFG_FORCE_MS_POS 28u /* RW */ 455 #define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03u 456 #define MCHP_ESPI_FC_CFG_FORCE_MS_MASK \ 457 SHLU32(MCHP_ESPI_FC_CFG_FORCE_MS_MASK0, MCHP_ESPI_FC_CFG_FORCE_MS_POS) 458 /* Host (eSPI Master) can select MAFS or SAFS */ 459 #define MCHP_ESPI_FC_CFG_FORCE_NONE 0u 460 /* EC forces eSPI slave HW to only allow MAFS */ 461 #define MCHP_ESPI_FC_CFG_FORCE_MAFS \ 462 SHLU32(0x02u, MCHP_ESPI_FC_CFG_FORCE_MS_POS) 463 /* EC forces eSPI slave HW to only allow SAFS */ 464 #define MCHP_ESPI_FC_CFG_FORCE_SAFS \ 465 SHLU32(0x03u, MCHP_ESPI_FC_CFG_FORCE_MS_POS) 466 467 /* FC STS */ 468 #define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u /* RO */ 469 #define MCHP_ESPI_FC_STS_CHAN_EN BIT(MCHP_ESPI_FC_STS_CHAN_EN_POS) 470 471 #define MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS 1u /* RW1C */ 472 #define MCHP_ESPI_FC_STS_CHAN_EN_CHG BIT(MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS) 473 474 #define MCHP_ESPI_FC_STS_DONE_POS 2u /* RW1C */ 475 #define MCHP_ESPI_FC_STS_DONE BIT(MCHP_ESPI_FC_STS_DONE_POS) 476 #define MCHP_ESPI_FC_STS_MDIS_POS 3u /* RW1C */ 477 #define MCHP_ESPI_FC_STS_MDIS BIT(MCHP_ESPI_FC_STS_MDIS_POS) 478 #define MCHP_ESPI_FC_STS_IBERR_POS 4u /* RW1C */ 479 #define MCHP_ESPI_FC_STS_IBERR BIT(MCHP_ESPI_FC_STS_IBERR_POS) 480 #define MCHP_ESPI_FC_STS_ABS_POS 5u /* RW1C */ 481 #define MCHP_ESPI_FC_STS_ABS BIT(MCHP_ESPI_FC_STS_ABS_POS) 482 #define MCHP_ESPI_FC_STS_OVRUN_POS 6u /* RW1C */ 483 #define MCHP_ESPI_FC_STS_OVRUN BIT(MCHP_ESPI_FC_STS_OVRUN_POS) 484 #define MCHP_ESPI_FC_STS_INC_POS 7u /* RW1C */ 485 #define MCHP_ESPI_FC_STS_INC BIT(MCHP_ESPI_FC_STS_INC_POS) 486 #define MCHP_ESPI_FC_STS_FAIL_POS 8u /* RW1C */ 487 #define MCHP_ESPI_FC_STS_FAIL BIT(MCHP_ESPI_FC_STS_FAIL_POS) 488 #define MCHP_ESPI_FC_STS_OVFL_POS 9u /* RW1C */ 489 #define MCHP_ESPI_FC_STS_OVFL BIT(MCHP_ESPI_FC_STS_OVFL_POS) 490 #define MCHP_ESPI_FC_STS_BADREQ_POS 11u /* RW1C */ 491 #define MCHP_ESPI_FC_STS_BADREQ BIT(MCHP_ESPI_FC_STS_BADREQ_POS) 492 493 #define MCHP_ESPI_FC_STS_ALL_RW1C 0x0bfeu 494 495 /*---- MCHP_ESPI_IO_BAR_HOST - eSPI IO Host visible BAR registers ----*/ 496 497 /* 498 * IOBAR_INH_LSW/MSW 64-bit register: each bit = 1 inhibits an I/O BAR 499 * independent of the BAR's Valid bit. 500 * Logical Device Number = bit position. 501 */ 502 #define MCHP_ESPI_IOBAR_LDN_MBOX 0u 503 #define MCHP_ESPI_IOBAR_LDN_KBC 1u 504 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_0 2u 505 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_1 3u 506 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_2 4u 507 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_3 5u 508 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_4 6u 509 #define MCHP_ESPI_IOBAR_LDN_ACPI_PM1 7u 510 #define MCHP_ESPI_IOBAR_LDN_PORT92 8u 511 #define MCHP_ESPI_IOBAR_LDN_UART_0 9u 512 #define MCHP_ESPI_IOBAR_LDN_UART_1 10u 513 #define MCHP_ESPI_IOBAR_LDN_IOC 13u 514 #define MCHP_ESPI_IOBAR_LDN_MEM 14u 515 #define MCHP_ESPI_IOBAR_LDN_GLUE_LOG 15u 516 #define MCHP_ESPI_IOBAR_LDN_EMI_0 16u 517 #define MCHP_ESPI_IOBAR_LDN_EMI_1 17u 518 #define MCHP_ESPI_IOBAR_LDN_EMI_2 18u 519 #define MCHP_ESPI_IOBAR_LDN_RTC 20u 520 #define MCHP_ESPI_IOBAR_LDN_P80CAP_0 32u /* BDP Port80 Capture */ 521 #define MCHP_ESPI_IOBAR_LDN_P80CAP_1 31u /* BDP Alias Capture */ 522 #define MCHP_ESPI_IOBAR_LDN_T32B 47u 523 #define MCHP_ESPI_IOBAR_LDN_LASIC 48u 524 525 /* 526 * IOBAR_INIT: Default address of I/O Plug and Play Super-IO index/data 527 * configuration registers. (Defaults to 0x2E/0x2F) 528 */ 529 #define MCHP_ESPI_IOBAR_INIT_DFLT 0x2eu 530 531 /* 532 * EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual 533 * SERIRQ slot is configured in MCHP_ESPI_IO_SIRQ.EC_SIRQ 534 */ 535 #define MCHP_ESPI_EC_IRQ_GEN (1u << 0) 536 537 /* 32-bit Host IO BAR */ 538 #define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u 539 #define MCHP_ESPI_IO_BAR_HOST_VALID \ 540 BIT(MCHP_ESPI_IO_BAR_HOST_VALID_POS) 541 #define MCHP_ESPI_IO_BAR_HOST_ADDR_POS 16u 542 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xffffu 543 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK 0xffff0000u 544 545 /* Offsets from first SIRQ */ 546 #define MCHP_ESPI_SIRQ_MBOX_SIRQ 0u 547 #define MCHP_ESPI_SIRQ_MBOX_SMI 1u 548 #define MCHP_ESPI_SIRQ_KBC_KIRQ 2u 549 #define MCHP_ESPI_SIRQ_KBC_MIRQ 3u 550 #define MCHP_ESPI_SIRQ_ACPI_EC0 4u 551 #define MCHP_ESPI_SIRQ_ACPI_EC1 5u 552 #define MCHP_ESPI_SIRQ_ACPI_EC2 6u 553 #define MCHP_ESPI_SIRQ_ACPI_EC3 7u 554 #define MCHP_ESPI_SIRQ_ACPI_EC4 8u 555 #define MCHP_ESPI_SIRQ_UART0 9u 556 #define MCHP_ESPI_SIRQ_UART1 10u 557 #define MCHP_ESPI_SIRQ_EMI0_HOST 11u 558 #define MCHP_ESPI_SIRQ_EMI0_E2H 12u 559 #define MCHP_ESPI_SIRQ_EMI1_HOST 13u 560 #define MCHP_ESPI_SIRQ_EMI1_E2H 14u 561 #define MCHP_ESPI_SIRQ_EMI2_HOST 15u 562 #define MCHP_ESPI_SIRQ_EMI2_E2H 16u 563 #define MCHP_ESPI_SIRQ_RTC 17u 564 #define MCHP_ESPI_SIRQ_EC 18u 565 #define MCHP_ESPI_SIRQ_RSVD19 19u 566 #define MCHP_ESPI_SIRQ_MAX 20u 567 568 /* 569 * Values for Logical Device SIRQ registers. 570 * Unless disabled each logical device must have a unique value 571 * programmed to its SIRQ register. 572 * Values 0x00u through 0x7Fu are sent using VWire host index 0x00 573 * Values 0x80h through 0xFEh are sent using VWire host index 0x01 574 * All registers reset default is 0xFFu (disabled). 575 */ 576 #define MCHP_ESPI_IO_SIRQ_DIS 0xFFu 577 578 /* eSPI Memory component registers */ 579 /* BM_STS */ 580 #define MCHP_ESPI_BM_STS_DONE_1_POS 0u /* RW1C */ 581 #define MCHP_ESPI_BM_STS_DONE_1 BIT(MCHP_ESPI_BM_STS_DONE_1_POS) 582 #define MCHP_ESPI_BM_STS_BUSY_1_POS 1u /* RO */ 583 #define MCHP_ESPI_BM_STS_BUSY_1 BIT(MCHP_ESPI_BM_STS_BUSY_1_POS) 584 #define MCHP_ESPI_BM_STS_AB_EC_1_POS 2u /* RW1C */ 585 #define MCHP_ESPI_BM_STS_AB_EC_1 BIT(MCHP_ESPI_BM_STS_AB_EC_1_POS) 586 #define MCHP_ESPI_BM_STS_AB_HOST_1_POS 3u /* RW1C */ 587 #define MCHP_ESPI_BM_STS_AB_HOST_1 BIT(MCHP_ESPI_BM_STS_AB_HOST_1_POS) 588 #define MCHP_ESPI_BM_STS_AB_CH2_1_POS 4u /* RW1C */ 589 #define MCHP_ESPI_BM_STS_CH2_AB_1 BIT(MCHP_ESPI_BM_STS_AB_CH2_1_POS) 590 #define MCHP_ESPI_BM_STS_OVFL_1_POS 5u /* RW1C */ 591 #define MCHP_ESPI_BM_STS_OVFL_1_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_1_POS) 592 #define MCHP_ESPI_BM_STS_OVRUN_1_POS 6u /* RW1C */ 593 #define MCHP_ESPI_BM_STS_OVRUN_1_CH2 BIT(MCHP_ESPI_BM_STS_OVRUN_1_POS) 594 #define MCHP_ESPI_BM_STS_INC_1_POS 7u /* RW1C */ 595 #define MCHP_ESPI_BM_STS_INC_1 BIT(MCHP_ESPI_BM_STS_INC_1_POS) 596 #define MCHP_ESPI_BM_STS_FAIL_1_POS 8u /* RW1C */ 597 #define MCHP_ESPI_BM_STS_FAIL_1 BIT(MCHP_ESPI_BM_STS_FAIL_1_POS) 598 #define MCHP_ESPI_BM_STS_IBERR_1_POS 9u /* RW1C */ 599 #define MCHP_ESPI_BM_STS_IBERR_1 BIT(MCHP_ESPI_BM_STS_IBERR_1_POS) 600 #define MCHP_ESPI_BM_STS_BADREQ_1_POS 11u /* RW1C */ 601 #define MCHP_ESPI_BM_STS_BADREQ_1 BIT(MCHP_ESPI_BM_STS_BADREQ_1_POS) 602 #define MCHP_ESPI_BM_STS_DONE_2_POS 16u /* RW1C */ 603 #define MCHP_ESPI_BM_STS_DONE_2 BIT(MCHP_ESPI_BM_STS_DONE_2_POS) 604 #define MCHP_ESPI_BM_STS_BUSY_2_POS 17u /* RO */ 605 #define MCHP_ESPI_BM_STS_BUSY_2 BIT(MCHP_ESPI_BM_STS_BUSY_2_POS) 606 #define MCHP_ESPI_BM_STS_AB_EC_2_POS 18u /* RW1C */ 607 #define MCHP_ESPI_BM_STS_AB_EC_2 BIT(MCHP_ESPI_BM_STS_AB_EC_2_POS) 608 #define MCHP_ESPI_BM_STS_AB_HOST_2_POS 19u /* RW1C */ 609 #define MCHP_ESPI_BM_STS_AB_HOST_2 BIT(MCHP_ESPI_BM_STS_AB_HOST_2_POS) 610 #define MCHP_ESPI_BM_STS_AB_CH1_2_POS 20u /* RW1C */ 611 #define MCHP_ESPI_BM_STS_AB_CH1_2 BIT(MCHP_ESPI_BM_STS_AB_CH1_2_POS) 612 #define MCHP_ESPI_BM_STS_OVFL_2_POS 21u /* RW1C */ 613 #define MCHP_ESPI_BM_STS_OVFL_2_CH2 BIT(MCHP_ESPI_BM_STS_OVFL_2_POS) 614 #define MCHP_ESPI_BM_STS_OVRUN_2_POS 22u /* RW1C */ 615 #define MCHP_ESPI_BM_STS_OVRUN_CH2_2 BIT(MCHP_ESPI_BM_STS_OVRUN_2_POS) 616 #define MCHP_ESPI_BM_STS_INC_2_POS 23u /* RW1C */ 617 #define MCHP_ESPI_BM_STS_INC_2 BIT(MCHP_ESPI_BM_STS_INC_2_POS) 618 #define MCHP_ESPI_BM_STS_FAIL_2_POS 24u /* RW1C */ 619 #define MCHP_ESPI_BM_STS_FAIL_2 BIT(MCHP_ESPI_BM_STS_FAIL_2_POS) 620 #define MCHP_ESPI_BM_STS_IBERR_2_POS 25u /* RW1C */ 621 #define MCHP_ESPI_BM_STS_IBERR_2 BIT(MCHP_ESPI_BM_STS_IBERR_2_POS) 622 #define MCHP_ESPI_BM_STS_BADREQ_2_POS 27u /* RW1C */ 623 #define MCHP_ESPI_BM_STS_BADREQ_2 BIT(MCHP_ESPI_BM_STS_BADREQ_2_POS) 624 625 #define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0bfdu 626 #define MCHP_ESPI_BM_STS_ALL_RW1C_2 0x0bfd0000u 627 628 /* BM_IEN */ 629 #define MCHP_ESPI_BM1_IEN_DONE_POS 0u 630 #define MCHP_ESPI_BM1_IEN_DONE BIT(MCHP_ESPI_BM1_IEN_DONE_POS) 631 #define MCHP_ESPI_BM2_IEN_DONE_POS 16u 632 #define MCHP_ESPI_BM2_IEN_DONE BIT(MCHP_ESPI_BM2_IEN_DONE_POS) 633 634 /* BM_CFG */ 635 #define MCHP_ESPI_BM1_CFG_TAG_POS 0u 636 #define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0fu 637 #define MCHP_ESPI_BM1_CFG_TAG_MASK 0x0fu 638 #define MCHP_ESPI_BM2_CFG_TAG_POS 16u 639 #define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0fu 640 #define MCHP_ESPI_BM2_CFG_TAG_MASK 0x0f0000u 641 642 /* BM1_CTRL */ 643 #define MCHP_ESPI_BM1_CTRL_START_POS 0u /* WO */ 644 #define MCHP_ESPI_BM1_CTRL_START BIT(MCHP_ESPI_BM1_CTRL_START_POS) 645 #define MCHP_ESPI_BM1_CTRL_ABORT_POS 1u /* WO */ 646 #define MCHP_ESPI_BM1_CTRL_ABORT BIT(MCHP_ESPI_BM1_CTRL_ABORT_POS) 647 #define MCHP_ESPI_BM1_CTRL_EN_INC_POS 2u /* RW */ 648 #define MCHP_ESPI_BM1_CTRL_EN_INC BIT(MCHP_ESPI_BM1_CTRL_EN_INC_POS) 649 #define MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS 3u /* RW */ 650 #define MCHP_ESPI_BM1_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS) 651 #define MCHP_ESPI_BM1_CTRL_CTYPE_POS 8u 652 #define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03u 653 #define MCHP_ESPI_BM1_CTRL_CTYPE_MASK \ 654 SHLU32(MCHP_ESPI_BM1_CTRL_CTYPE_MASK0, MCHP_ESPI_BM1_CTRL_CTYPE_POS) 655 #define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 0x00u 656 #define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR32 \ 657 SHLU32(0x01u, MCHP_ESPI_BM1_CTRL_CTYPE_POS) 658 #define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR64 \ 659 SHLU32(0x02u, MCHP_ESPI_BM1_CTRL_CTYPE_POS) 660 #define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR64 \ 661 SHLU32(0x03u, MCHP_ESPI_BM1_CTRL_CTYPE_POS) 662 #define MCHP_ESPI_BM1_CTRL_LEN_POS 16u 663 #define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1fffu 664 #define MCHP_ESPI_BM1_CTRL_LEN_MASK 0x1fff0000u 665 666 /* BM1_EC_ADDR_LSW */ 667 #define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xfffffffcu 668 669 /* BM2_CTRL */ 670 #define MCHP_ESPI_BM2_CTRL_START_POS 0u /* WO */ 671 #define MCHP_ESPI_BM2_CTRL_START BIT(MCHP_ESPI_BM2_CTRL_START_POS) 672 #define MCHP_ESPI_BM2_CTRL_ABORT_POS 1u /* WO */ 673 #define MCHP_ESPI_BM2_CTRL_ABORT BIT(MCHP_ESPI_BM2_CTRL_ABORT_POS) 674 #define MCHP_ESPI_BM2_CTRL_EN_INC_POS 2u /* RW */ 675 #define MCHP_ESPI_BM2_CTRL_EN_INC BIT(MCHP_ESPI_BM2_CTRL_EN_INC_POS) 676 #define MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS 3u /* RW */ 677 #define MCHP_ESPI_BM2_CTRL_WAIT_NB2 BIT(MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS) 678 #define MCHP_ESPI_BM2_CTRL_CTYPE_POS 8u 679 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03u 680 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK 0x0300u 681 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 0x00u 682 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 0x0100u 683 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 0x0200u 684 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 0x0300u 685 #define MCHP_ESPI_BM2_CTRL_LEN_POS 16u 686 #define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1fffu 687 #define MCHP_ESPI_BM2_CTRL_LEN_MASK 0x1fff0000u 688 689 /* BM2_EC_ADDR_LSW */ 690 #define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xfffffffcu 691 692 /* 693 * MCHP_ESPI_MEM_BAR_EC @ 0x400F3930 694 * Half-word H0 of each EC Memory BAR contains 695 * Memory BAR memory address mask bits in bits[7:0] 696 * Logical Device Number in bits[13:8] 697 */ 698 #define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u 699 #define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xffu 700 #define MCHP_ESPI_EBAR_H0_LDN_POS 8u 701 #define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3fu 702 #define MCHP_ESPI_EBAR_H0_LDN_MASK 0x3f00u 703 704 /* 705 * MCHP_ESPI_MEM_BAR_HOST @ 0x400F3B30 706 * Each Host BAR contains: 707 * bit[0] (RW) = Valid bit 708 * bits[15:1] = Reserved, read-only 0 709 * bits[47:16] (RW) = bits[31:0] of the Host Memory address. 710 */ 711 712 /* Memory BAR Host address valid */ 713 #define MCHP_ESPI_HBAR_VALID_POS 0u 714 #define MCHP_ESPI_HBAR_VALID_MASK 0x01u 715 /* 716 * Host address is in bits[47:16] of the HBAR 717 * HBAR's are spaced every 10 bytes (80 bits) but 718 * only implement bits[47:0] 719 */ 720 #define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */ 721 /* 32-bit Host Address */ 722 #define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */ 723 #define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */ 724 #define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */ 725 #define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */ 726 727 #define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u 728 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01u 729 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01u 730 #define MCHP_EC_SRAM_BAR_H0_VALID 0x01u 731 #define MCHP_EC_SRAM_BAR_H0_ACCESS_POS 1u 732 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03u 733 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK 0x06u 734 #define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE 0x00u 735 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RO 0x02u 736 #define MCHP_EC_SRAM_BAR_H0_ACCESS_WO 0x04u 737 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RW 0x06u 738 #define MCHP_EC_SRAM_BAR_H0_SIZE_POS 4u 739 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0fu 740 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK 0xf0u 741 #define MCHP_EC_SRAM_BAR_H0_SIZE_1B 0x00u 742 #define MCHP_EC_SRAM_BAR_H0_SIZE_2B 0x10u 743 #define MCHP_EC_SRAM_BAR_H0_SIZE_4B 0x20u 744 #define MCHP_EC_SRAM_BAR_H0_SIZE_8B 0x30u 745 #define MCHP_EC_SRAM_BAR_H0_SIZE_16B 0x40u 746 #define MCHP_EC_SRAM_BAR_H0_SIZE_32B 0x50u 747 #define MCHP_EC_SRAM_BAR_H0_SIZE_64B 0x60u 748 #define MCHP_EC_SRAM_BAR_H0_SIZE_128B 0x70u 749 #define MCHP_EC_SRAM_BAR_H0_SIZE_256B 0x80u 750 #define MCHP_EC_SRAM_BAR_H0_SIZE_512B 0x90u 751 #define MCHP_EC_SRAM_BAR_H0_SIZE_1KB 0xa0u 752 #define MCHP_EC_SRAM_BAR_H0_SIZE_2KB 0xb0u 753 #define MCHP_EC_SRAM_BAR_H0_SIZE_4KB 0xc0u 754 #define MCHP_EC_SRAM_BAR_H0_SIZE_8KB 0xd0u 755 #define MCHP_EC_SRAM_BAR_H0_SIZE_16KB 0xe0u 756 #define MCHP_EC_SRAM_BAR_H0_SIZE_32KB 0xf0u 757 /* EC and Host SRAM BAR start offset of EC or Host memory address */ 758 #define MCHP_EC_SRAM_BAR_MADDR_OFS1 2u 759 #define MCHP_EC_SRAM_BAR_MADDR_OFS2 4u 760 761 /* Interfaces to any C modules */ 762 #ifdef __cplusplus 763 extern "C" { 764 #endif 765 766 /* Array indices for eSPI IO BAR Host and EC-only register structures */ 767 enum espi_io_bar_idx { 768 IOB_IOC = 0, 769 IOB_MEM, 770 IOB_MBOX, 771 IOB_KBC, 772 IOB_ACPI_EC0, 773 IOB_ACPI_EC1, 774 IOB_ACPI_EC2, 775 IOB_ACPI_EC3, 776 IOB_ACPI_EC4, 777 IOB_ACPI_PM1, 778 IOB_PORT92, 779 IOB_UART0, 780 IOB_UART1, 781 IOB_EMI0, 782 IOB_EMI1, 783 IOB_EMI2, 784 IOB_P80BD, /* MEC152x IOB_P80_CAP0 */ 785 IOB_P80BD_ALIAS, /* MEC152x IOB_P80_CAP1 */ 786 IOB_RTC, 787 IOB_RSVD19, 788 IOB_T32B, 789 IOB_RSVD21, 790 IOB_GLUE, 791 IOB_MAX 792 }; 793 794 /** @brief Serial IRQ byte register indices */ 795 enum espi_io_sirq_idx { 796 SIRQ_MBOX = 0, SIRQ_MBOX_SMI, SIRQ_KBC_KIRQ, 797 SIRQ_KBC_MIRQ, SIRQ_ACPI_EC0_OBF, SIRQ_ACPI_EC1_OBF, 798 SIRQ_ACPI_EC2_OBF, SIRQ_ACPI_EC3_OBF, SIRQ_ACPI_EC4_OBF, 799 SIRQ_UART0, SIRQ_UART1, SIRQ_EMI0_HEV, 800 SIRQ_EMI0_E2H, SIRQ_EMI1_HEV, SIRQ_EMI1_E2H, 801 SIRQ_EMI2_HEV, SIRQ_EMI2_E2H, SIRQ_RTC, 802 SIRQ_EC, SIRQ_MAX 803 }; 804 805 enum espi_mem_bar_idx { 806 MEMB_MBOX = 0, 807 MEMB_ACPI_EC0, 808 MEMB_ACPI_EC1, 809 MEMB_ACPI_EC2, 810 MEMB_ACPI_EC3, 811 MEMB_ACPI_EC4, 812 MEMB_EMI0, 813 MEMB_EMI1, 814 MEMB_EMI2, 815 MEMB_T32B, 816 MEMB_MAX 817 }; 818 819 /* eSPI */ 820 struct espi_io_mbar { /* 80-bit register */ 821 volatile uint16_t LDN_MASK; 822 volatile uint16_t RESERVED[4]; 823 }; /* Size = 10 (0xa) */ 824 825 struct espi_mbar_host { 826 volatile uint16_t VALID; 827 volatile uint16_t HADDR_LSH; 828 volatile uint16_t HADDR_MSH; 829 volatile uint16_t RESERVED[2]; 830 }; /* Size = 10 (0xa) */ 831 832 struct espi_sram_bar { 833 volatile uint16_t VACCSZ; 834 volatile uint16_t EC_SRAM_BASE_LSH; 835 volatile uint16_t EC_SRAM_BASE_MSH; 836 volatile uint16_t RESERVED[2]; 837 }; /* Size = 10 (0xa) */ 838 839 struct espi_sram_host_bar { 840 volatile uint16_t ACCSZ; 841 volatile uint16_t HBASE_LSH; 842 volatile uint16_t HBASE_MSH; 843 volatile uint16_t RESERVED[2]; 844 }; /* Size = 10 (0xa) */ 845 846 /** @brief eSPI Capabilities, I/O and Memory components in one structure */ 847 struct espi_iom_regs { /* @ 0x400F3400 */ 848 volatile uint8_t RTIDX; /* @ 0x0000 */ 849 volatile uint8_t RTDAT; /* @ 0x0001 */ 850 volatile uint16_t RESERVED; 851 volatile uint32_t RESERVED1[63]; 852 volatile uint32_t PCLC[3]; /* @ 0x0100 */ 853 volatile uint32_t PCERR[2]; /* @ 0x010C */ 854 volatile uint32_t PCSTS; /* @ 0x0114 */ 855 volatile uint32_t PCIEN; /* @ 0x0118 */ 856 volatile uint32_t RESERVED2; 857 volatile uint32_t PCBINH[2]; /* @ 0x0120 */ 858 volatile uint32_t PCBINIT; /* @ 0x0128 */ 859 volatile uint32_t PCECIRQ; /* @ 0x012C */ 860 volatile uint32_t PCCKNP; /* @ 0x0130 */ 861 volatile uint32_t PCBARI[29]; /* @ 0x0134 */ 862 volatile uint32_t RESERVED3[30]; 863 volatile uint32_t PCLTRSTS; /* @ 0x0220 */ 864 volatile uint32_t PCLTREN; /* @ 0x0224 */ 865 volatile uint32_t PCLTRCTL; /* @ 0x0228 */ 866 volatile uint32_t PCLTRM; /* @ 0x022C */ 867 volatile uint32_t RESERVED4[4]; 868 volatile uint32_t OOBRXA[2]; /* @ 0x0240 */ 869 volatile uint32_t OOBTXA[2]; /* @ 0x0248 */ 870 volatile uint32_t OOBRXL; /* @ 0x0250 */ 871 volatile uint32_t OOBTXL; /* @ 0x0254 */ 872 volatile uint32_t OOBRXC; /* @ 0x0258 */ 873 volatile uint32_t OOBRXIEN; /* @ 0x025C */ 874 volatile uint32_t OOBRXSTS; /* @ 0x0260 */ 875 volatile uint32_t OOBTXC; /* @ 0x0264 */ 876 volatile uint32_t OOBTXIEN; /* @ 0x0268 */ 877 volatile uint32_t OOBTXSTS; /* @ 0x026C */ 878 volatile uint32_t RESERVED5[4]; 879 volatile uint32_t FCFA[2]; /* @ 0x0280 */ 880 volatile uint32_t FCBA[2]; /* @ 0x0288 */ 881 volatile uint32_t FCLEN; /* @ 0x0290 */ 882 volatile uint32_t FCCTL; /* @ 0x0294 */ 883 volatile uint32_t FCIEN; /* @ 0x0298 */ 884 volatile uint32_t FCCFG; /* @ 0x029C */ 885 volatile uint32_t FCSTS; /* @ 0x02A0 */ 886 volatile uint32_t RESERVED6[3]; 887 volatile uint32_t VWSTS; /* @ 0x02B0 */ 888 volatile uint32_t RESERVED7[11]; 889 volatile uint8_t CAPID; /* @ 0x02E0 */ 890 volatile uint8_t CAP0; /* @ 0x02E1 */ 891 volatile uint8_t CAP1; /* @ 0x02E2 */ 892 volatile uint8_t CAPPC; /* @ 0x02E3 */ 893 volatile uint8_t CAPVW; /* @ 0x02E4 */ 894 volatile uint8_t CAPOOB; /* @ 0x02E5 */ 895 volatile uint8_t CAPFC; /* @ 0x02E6 */ 896 volatile uint8_t PCRDY; /* @ 0x02E7 */ 897 volatile uint8_t OOBRDY; /* @ 0x02E8 */ 898 volatile uint8_t FCRDY; /* @ 0x02E9 */ 899 volatile uint8_t ERIS; /* @ 0x02EA */ 900 volatile uint8_t ERIE; /* @ 0x02EB */ 901 volatile uint8_t PLTSRC; /* @ 0x02EC */ 902 volatile uint8_t VWRDY; /* @ 0x02ED */ 903 volatile uint8_t SAFEBS; /* @ 0x02EE */ 904 volatile uint8_t RESERVED8; 905 volatile uint32_t RESERVED9[16]; 906 volatile uint32_t ACTV; /* @ 0x0330 */ 907 volatile uint32_t IOHBAR[29]; /* @ 0x0334 */ 908 volatile uint32_t RESERVED10; 909 volatile uint8_t SIRQ[19]; /* @ 0x03ac */ 910 volatile uint8_t RESERVED11; 911 volatile uint32_t RESERVED12[12]; 912 volatile uint32_t VWERREN; /* @ 0x03f0 */ 913 volatile uint32_t RESERVED13[79]; 914 struct espi_io_mbar MBAR[10]; /* @ 0x0530 */ 915 volatile uint32_t RESERVED14[6]; 916 struct espi_sram_bar SRAMBAR[2]; /* @ 0x05AC */ 917 volatile uint32_t RESERVED15[16]; 918 volatile uint32_t BM_STATUS; /* @ 0x0600 */ 919 volatile uint32_t BM_IEN; /* @ 0x0604 */ 920 volatile uint32_t BM_CONFIG; /* @ 0x0608 */ 921 volatile uint32_t RESERVED16; 922 volatile uint32_t BM_CTRL1; /* @ 0x0610 */ 923 volatile uint32_t BM_HADDR1_LSW; /* @ 0x0614 */ 924 volatile uint32_t BM_HADDR1_MSW; /* @ 0x0618 */ 925 volatile uint32_t BM_EC_ADDR1_LSW; /* @ 0x061C */ 926 volatile uint32_t BM_EC_ADDR1_MSW; /* @ 0x0620 */ 927 volatile uint32_t BM_CTRL2; /* @ 0x0624 */ 928 volatile uint32_t BM_HADDR2_LSW; /* @ 0x0628 */ 929 volatile uint32_t BM_HADDR2_MSW; /* @ 0x062C */ 930 volatile uint32_t BM_EC_ADDR2_LSW; /* @ 0x0630 */ 931 volatile uint32_t BM_EC_ADDR2_MSW; /* @ 0x0634 */ 932 volatile uint32_t RESERVED17[62]; 933 struct espi_mbar_host HMBAR[10]; /* @ 0x0730 */ 934 volatile uint32_t RESERVED18[6]; 935 struct espi_sram_host_bar HSRAMBAR[2]; /* @ 0x07AC */ 936 }; /* Size = 1984 (0x7c0) */ 937 938 #ifdef __cplusplus 939 } 940 #endif 941 942 #endif /* #ifndef _MEC172X_ESPI_IO_H */ 943
