1 /*
2 * Copyright (c) 2017 Christer Weinigel.
3 * Copyright (c) 2017, I-SENSE group of ICCS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @file
10 * @brief USB device controller shim driver for STM32 devices
11 *
12 * This driver uses the STM32 Cube low level drivers to talk to the USB
13 * device controller on the STM32 family of devices using the
14 * STM32Cube HAL layer.
15 */
16
17 #include <soc.h>
18 #include <stm32_ll_bus.h>
19 #include <stm32_ll_pwr.h>
20 #include <stm32_ll_rcc.h>
21 #include <stm32_ll_system.h>
22 #include <string.h>
23 #include <usb/usb_device.h>
24 #include <drivers/clock_control/stm32_clock_control.h>
25 #include <sys/util.h>
26 #include <drivers/gpio.h>
27 #include <pinmux/pinmux_stm32.h>
28 #include "stm32_hsem.h"
29
30 #define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
31 #include <logging/log.h>
32 LOG_MODULE_REGISTER(usb_dc_stm32);
33
34 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
35 #error "Only one interface should be enabled at a time, OTG FS or OTG HS"
36 #endif
37
38 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
39 #define DT_DRV_COMPAT st_stm32_otghs
40 #define USB_IRQ_NAME otghs
41 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
42 #define DT_DRV_COMPAT st_stm32_otgfs
43 #define USB_IRQ_NAME otgfs
44 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
45 #define DT_DRV_COMPAT st_stm32_usb
46 #define USB_IRQ_NAME usb
47 #if DT_INST_NODE_HAS_PROP(0, enable_pin_remap)
48 #define USB_ENABLE_PIN_REMAP DT_INST_PROP(0, enable_pin_remap)
49 #endif
50 #endif
51
52 #define USB_BASE_ADDRESS DT_INST_REG_ADDR(0)
53 #define USB_IRQ DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, irq)
54 #define USB_IRQ_PRI DT_INST_IRQ_BY_NAME(0, USB_IRQ_NAME, priority)
55 #define USB_NUM_BIDIR_ENDPOINTS DT_INST_PROP(0, num_bidir_endpoints)
56 #define USB_RAM_SIZE DT_INST_PROP(0, ram_size)
57 #define USB_CLOCK_BITS DT_INST_CLOCKS_CELL(0, bits)
58 #define USB_CLOCK_BUS DT_INST_CLOCKS_CELL(0, bus)
59 #if DT_INST_NODE_HAS_PROP(0, maximum_speed)
60 #define USB_MAXIMUM_SPEED DT_INST_PROP(0, maximum_speed)
61 #endif
62 static const struct soc_gpio_pinctrl usb_pinctrl[] =
63 ST_STM32_DT_INST_PINCTRL(0, 0);
64
65
66 #define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
67 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
68
69 /*
70 * USB, USB_OTG_FS and USB_DRD_FS are defined in STM32Cube HAL and allows to
71 * distinguish between two kind of USB DC. STM32 F0, F3, L0 and G4 series
72 * support USB device controller. STM32 F4 and F7 series support USB_OTG_FS
73 * device controller. STM32 F1 and L4 series support either USB or USB_OTG_FS
74 * device controller.STM32 G0 series supports USB_DRD_FS device controller.
75 *
76 * WARNING: Don't mix USB defined in STM32Cube HAL and CONFIG_USB_* from Zephyr
77 * Kconfig system.
78 */
79 #if defined(USB) || defined(USB_DRD_FS)
80
81 #define EP0_MPS 64U
82 #define EP_MPS 64U
83
84 /*
85 * USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
86 * per endpoint.
87 *
88 */
89 #define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
90
91 #else /* USB_OTG_FS */
92
93 /*
94 * STM32L4 series USB LL API doesn't provide HIGH and HIGH_IN_FULL speed
95 * defines.
96 */
97 #if defined(CONFIG_SOC_SERIES_STM32L4X)
98 #define USB_OTG_SPEED_HIGH 0U
99 #define USB_OTG_SPEED_HIGH_IN_FULL 1U
100 #endif /* CONFIG_SOC_SERIES_STM32L4X */
101
102 #define EP0_MPS USB_OTG_MAX_EP0_SIZE
103
104 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
105 #define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
106 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
107 #define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
108 #endif
109
110 /* We need one RX FIFO and n TX-IN FIFOs */
111 #define FIFO_NUM (1 + USB_NUM_BIDIR_ENDPOINTS)
112
113 /* 4-byte words FIFO */
114 #define FIFO_WORDS (USB_RAM_SIZE / 4)
115
116 /* Allocate FIFO memory evenly between the FIFOs */
117 #define FIFO_EP_WORDS (FIFO_WORDS / FIFO_NUM)
118
119 #endif /* USB */
120
121 /* Size of a USB SETUP packet */
122 #define SETUP_SIZE 8
123
124 /* Helper macros to make it easier to work with endpoint numbers */
125 #define EP0_IDX 0
126 #define EP0_IN (EP0_IDX | USB_EP_DIR_IN)
127 #define EP0_OUT (EP0_IDX | USB_EP_DIR_OUT)
128
129 /* Endpoint state */
130 struct usb_dc_stm32_ep_state {
131 uint16_t ep_mps; /** Endpoint max packet size */
132 uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
133 uint8_t ep_type; /** Endpoint type (STM32 HAL enum) */
134 uint8_t ep_stalled; /** Endpoint stall flag */
135 usb_dc_ep_callback cb; /** Endpoint callback function */
136 uint32_t read_count; /** Number of bytes in read buffer */
137 uint32_t read_offset; /** Current offset in read buffer */
138 struct k_sem write_sem; /** Write boolean semaphore */
139 };
140
141 /* Driver state */
142 struct usb_dc_stm32_state {
143 PCD_HandleTypeDef pcd; /* Storage for the HAL_PCD api */
144 usb_dc_status_callback status_cb; /* Status callback */
145 struct usb_dc_stm32_ep_state out_ep_state[USB_NUM_BIDIR_ENDPOINTS];
146 struct usb_dc_stm32_ep_state in_ep_state[USB_NUM_BIDIR_ENDPOINTS];
147 uint8_t ep_buf[USB_NUM_BIDIR_ENDPOINTS][EP_MPS];
148
149 #if defined(USB) || defined(USB_DRD_FS)
150 uint32_t pma_offset;
151 #endif /* USB */
152 };
153
154 static struct usb_dc_stm32_state usb_dc_stm32_state;
155
156 /* Internal functions */
157
usb_dc_stm32_get_ep_state(uint8_t ep)158 static struct usb_dc_stm32_ep_state *usb_dc_stm32_get_ep_state(uint8_t ep)
159 {
160 struct usb_dc_stm32_ep_state *ep_state_base;
161
162 if (USB_EP_GET_IDX(ep) >= USB_NUM_BIDIR_ENDPOINTS) {
163 return NULL;
164 }
165
166 if (USB_EP_DIR_IS_OUT(ep)) {
167 ep_state_base = usb_dc_stm32_state.out_ep_state;
168 } else {
169 ep_state_base = usb_dc_stm32_state.in_ep_state;
170 }
171
172 return ep_state_base + USB_EP_GET_IDX(ep);
173 }
174
usb_dc_stm32_isr(const void * arg)175 static void usb_dc_stm32_isr(const void *arg)
176 {
177 HAL_PCD_IRQHandler(&usb_dc_stm32_state.pcd);
178 }
179
180 #ifdef CONFIG_USB_DEVICE_SOF
HAL_PCD_SOFCallback(PCD_HandleTypeDef * hpcd)181 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
182 {
183 usb_dc_stm32_state.status_cb(USB_DC_SOF, NULL);
184 }
185 #endif
186
usb_dc_stm32_clock_enable(void)187 static int usb_dc_stm32_clock_enable(void)
188 {
189 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
190 struct stm32_pclken pclken = {
191 .bus = USB_CLOCK_BUS,
192 .enr = USB_CLOCK_BITS,
193 };
194
195 /*
196 * Some SoCs in STM32F0/L0/L4 series disable USB clock by
197 * default. We force USB clock source to MSI or PLL clock for this
198 * SoCs. However, if these parts have an HSI48 clock, use
199 * that instead. Example reference manual RM0360 for
200 * STM32F030x4/x6/x8/xC and STM32F070x6/xB.
201 */
202 #if defined(RCC_HSI48_SUPPORT) || \
203 defined(CONFIG_SOC_SERIES_STM32WBX) || \
204 defined(CONFIG_SOC_SERIES_STM32H7X)
205
206 /*
207 * In STM32L0 series, HSI48 requires VREFINT and its buffer
208 * with 48 MHz RC to be enabled.
209 * See ENREF_HSI48 in referenc maual RM0367 section10.2.3:
210 * "Reference control and status register (SYSCFG_CFGR3)"
211 */
212 #ifdef CONFIG_SOC_SERIES_STM32L0X
213 if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
214 LL_SYSCFG_VREFINT_EnableHSI48();
215 } else {
216 LOG_ERR("System Configuration Controller clock is "
217 "disabled. Unable to enable VREFINT which "
218 "is required by HSI48.");
219 }
220 #endif /* CONFIG_SOC_SERIES_STM32L0X */
221
222 z_stm32_hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
223
224 LL_RCC_HSI48_Enable();
225 while (!LL_RCC_HSI48_IsReady()) {
226 /* Wait for HSI48 to become ready */
227 }
228
229 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_HSI48);
230
231 #if !defined(CONFIG_SOC_SERIES_STM32WBX)
232 /* Specially for STM32WB, don't unlock the HSEM to prevent M0 core
233 * to disable HSI48 clock used for RNG.
234 */
235 z_stm32_hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);
236 #endif /* CONFIG_SOC_SERIES_STM32WBX */
237
238 #elif defined(LL_RCC_USB_CLKSOURCE_NONE)
239 /* When MSI is configured in PLL mode with a 32.768 kHz clock source,
240 * the MSI frequency can be automatically trimmed by hardware to reach
241 * better than ±0.25% accuracy. In this mode the MSI can feed the USB
242 * device. For now, we only use MSI for USB if not already used as
243 * system clock source.
244 */
245 #if STM32_MSI_PLL_MODE && !STM32_SYSCLK_SRC_MSI
246 LL_RCC_MSI_Enable();
247 while (!LL_RCC_MSI_IsReady()) {
248 /* Wait for MSI to become ready */
249 }
250 /* Force 48 MHz mode */
251 LL_RCC_MSI_EnableRangeSelection();
252 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_11);
253 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_MSI);
254 #else
255 if (LL_RCC_PLL_IsReady()) {
256 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL);
257 } else {
258 LOG_ERR("Unable to set USB clock source to PLL.");
259 }
260 #endif /* STM32_MSI_PLL_MODE && !STM32_SYSCLK_SRC_MSI */
261
262 #elif defined(RCC_CFGR_OTGFSPRE)
263 /* On STM32F105 and STM32F107 parts the USB OTGFSCLK is derived from
264 * PLL1, and must result in a 48 MHz clock... the options to achieve
265 * this are as below, controlled by the RCC_CFGR_OTGFSPRE bit.
266 * - PLLCLK * 2 / 2 i.e: PLLCLK == 48 MHz
267 * - PLLCLK * 2 / 3 i.e: PLLCLK == 72 MHz
268 *
269 * this requires that the system is running from PLLCLK
270 */
271 if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
272 switch (sys_clock_hw_cycles_per_sec()) {
273 case 48000000U:
274 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL_DIV_2);
275 break;
276 case 72000000U:
277 LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL_DIV_3);
278 break;
279 default:
280 LOG_ERR("Unable to set USB clock source (incompatible PLLCLK rate)");
281 return -EIO;
282 }
283 } else {
284 LOG_ERR("Unable to set USB clock source (not using PLL1)");
285 return -EIO;
286 }
287
288 #endif /* RCC_HSI48_SUPPORT / LL_RCC_USB_CLKSOURCE_NONE / RCC_CFGR_OTGFSPRE */
289
290 if (clock_control_on(clk, (clock_control_subsys_t *)&pclken) != 0) {
291 LOG_ERR("Unable to enable USB clock");
292 return -EIO;
293 }
294
295 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
296 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc)
297 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
298 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
299 #else
300 /* Disable ULPI interface (for external high-speed PHY) clock */
301 LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
302 LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
303 #endif
304 #endif
305
306 return 0;
307 }
308
309 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
usb_dc_stm32_get_maximum_speed(void)310 static uint32_t usb_dc_stm32_get_maximum_speed(void)
311 {
312 /*
313 * If max-speed is not passed via DT, set it to USB controller's
314 * maximum hardware capability.
315 */
316 #if USB_OTG_HS_EMB_PHY
317 uint32_t speed = USB_OTG_SPEED_HIGH;
318 #else
319 uint32_t speed = USB_OTG_SPEED_FULL;
320 #endif
321
322 #ifdef USB_MAXIMUM_SPEED
323
324 if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
325 speed = USB_OTG_SPEED_HIGH;
326 } else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
327 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
328 speed = USB_OTG_SPEED_HIGH_IN_FULL;
329 #else
330 speed = USB_OTG_SPEED_FULL;
331 #endif
332 } else {
333 LOG_DBG("Unsupported maximum speed defined in device tree. "
334 "USB controller will default to its maximum HW "
335 "capability");
336 }
337 #endif
338
339 return speed;
340 }
341 #endif /* USB_OTG_FS || USB_OTG_HS */
342
usb_dc_stm32_init(void)343 static int usb_dc_stm32_init(void)
344 {
345 HAL_StatusTypeDef status;
346 unsigned int i;
347
348 #if defined(USB) || defined(USB_DRD_FS)
349 #ifdef USB
350 usb_dc_stm32_state.pcd.Instance = USB;
351 #else
352 usb_dc_stm32_state.pcd.Instance = USB_DRD_FS;
353 #endif
354 usb_dc_stm32_state.pcd.Init.speed = PCD_SPEED_FULL;
355 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
356 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
357 usb_dc_stm32_state.pcd.Init.ep0_mps = PCD_EP0MPS_64;
358 usb_dc_stm32_state.pcd.Init.low_power_enable = 0;
359 #else /* USB_OTG_FS || USB_OTG_HS */
360 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
361 usb_dc_stm32_state.pcd.Instance = USB_OTG_HS;
362 #else
363 usb_dc_stm32_state.pcd.Instance = USB_OTG_FS;
364 #endif
365 usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
366 usb_dc_stm32_state.pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
367 #if USB_OTG_HS_EMB_PHY
368 usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
369 #else
370 usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
371 #endif
372 usb_dc_stm32_state.pcd.Init.ep0_mps = USB_OTG_MAX_EP0_SIZE;
373 usb_dc_stm32_state.pcd.Init.vbus_sensing_enable = DISABLE;
374
375 #ifndef CONFIG_SOC_SERIES_STM32F1X
376 usb_dc_stm32_state.pcd.Init.dma_enable = DISABLE;
377 #endif
378
379 #endif /* USB */
380
381 #ifdef CONFIG_USB_DEVICE_SOF
382 usb_dc_stm32_state.pcd.Init.Sof_enable = 1;
383 #endif /* CONFIG_USB_DEVICE_SOF */
384
385 #if defined(CONFIG_SOC_SERIES_STM32H7X)
386 /* Currently assuming FS mode. Need to disable the ULPI clock on USB2 and
387 * enable the FS clock. Need to make this dependent on HS or FS config.
388 */
389
390 LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
391 LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
392
393 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
394 LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
395
396 LL_PWR_EnableUSBVoltageDetector();
397
398 /* Per AN2606: USBREGEN not supported when running in FS mode. */
399 LL_PWR_DisableUSBReg();
400 while (!LL_PWR_IsActiveFlag_USB()) {
401 LOG_INF("PWR not active yet");
402 k_sleep(K_MSEC(100));
403 }
404 #endif
405
406 LOG_DBG("Pinctrl signals configuration");
407 status = stm32_dt_pinctrl_configure(usb_pinctrl,
408 ARRAY_SIZE(usb_pinctrl),
409 (uint32_t)usb_dc_stm32_state.pcd.Instance);
410 if (status < 0) {
411 LOG_ERR("USB pinctrl setup failed (%d)", status);
412 return status;
413 }
414
415 LOG_DBG("HAL_PCD_Init");
416 status = HAL_PCD_Init(&usb_dc_stm32_state.pcd);
417 if (status != HAL_OK) {
418 LOG_ERR("PCD_Init failed, %d", (int)status);
419 return -EIO;
420 }
421
422 LOG_DBG("HAL_PCD_Start");
423 status = HAL_PCD_Start(&usb_dc_stm32_state.pcd);
424 if (status != HAL_OK) {
425 LOG_ERR("PCD_Start failed, %d", (int)status);
426 return -EIO;
427 }
428
429 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_mps = EP0_MPS;
430 usb_dc_stm32_state.out_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
431 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_mps = EP0_MPS;
432 usb_dc_stm32_state.in_ep_state[EP0_IDX].ep_type = EP_TYPE_CTRL;
433
434 #if defined(USB) || defined(USB_DRD_FS)
435 /* Start PMA configuration for the endpoints after the BTABLE. */
436 usb_dc_stm32_state.pma_offset = USB_BTABLE_SIZE;
437
438 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
439 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
440 }
441 #else /* USB_OTG_FS */
442 /* TODO: make this dynamic (depending usage) */
443 HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, FIFO_EP_WORDS);
444 for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
445 HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i,
446 FIFO_EP_WORDS);
447 k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1);
448 }
449 #endif /* USB */
450
451 IRQ_CONNECT(USB_IRQ, USB_IRQ_PRI,
452 usb_dc_stm32_isr, 0, 0);
453 irq_enable(USB_IRQ);
454 return 0;
455 }
456
457 /* Zephyr USB device controller API implementation */
458
usb_dc_attach(void)459 int usb_dc_attach(void)
460 {
461 int ret;
462
463 LOG_DBG("");
464
465 #ifdef SYSCFG_CFGR1_USB_IT_RMP
466 /*
467 * STM32F302/F303: USB IRQ collides with CAN_1 IRQ (§14.1.3, RM0316)
468 * Remap IRQ by default to enable use of both IPs simultaneoulsy
469 * This should be done before calling any HAL function
470 */
471 if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
472 LL_SYSCFG_EnableRemapIT_USB();
473 } else {
474 LOG_ERR("System Configuration Controller clock is "
475 "disabled. Unable to enable IRQ remapping.");
476 }
477 #endif
478
479 /*
480 * For STM32F0 series SoCs on QFN28 and TSSOP20 packages enable PIN
481 * pair PA11/12 mapped instead of PA9/10 (e.g. stm32f070x6)
482 */
483 #if USB_ENABLE_PIN_REMAP == 1
484 if (LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_SYSCFG)) {
485 LL_SYSCFG_EnablePinRemap();
486 } else {
487 LOG_ERR("System Configuration Controller clock is "
488 "disabled. Unable to enable pin remapping.");
489 }
490 #endif
491
492 ret = usb_dc_stm32_clock_enable();
493 if (ret) {
494 return ret;
495 }
496
497 ret = usb_dc_stm32_init();
498 if (ret) {
499 return ret;
500 }
501
502 /*
503 * Required for at least STM32L4 devices as they electrically
504 * isolate USB features from VDDUSB. It must be enabled before
505 * USB can function. Refer to section 5.1.3 in DM00083560 or
506 * DM00310109.
507 */
508 #ifdef PWR_CR2_USV
509 #if defined(LL_APB1_GRP1_PERIPH_PWR)
510 if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
511 LL_PWR_EnableVddUSB();
512 } else {
513 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
514 LL_PWR_EnableVddUSB();
515 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
516 }
517 #else
518 LL_PWR_EnableVddUSB();
519 #endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
520 #endif /* PWR_CR2_USV */
521
522 return 0;
523 }
524
usb_dc_ep_set_callback(const uint8_t ep,const usb_dc_ep_callback cb)525 int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb)
526 {
527 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
528
529 LOG_DBG("ep 0x%02x", ep);
530
531 if (!ep_state) {
532 return -EINVAL;
533 }
534
535 ep_state->cb = cb;
536
537 return 0;
538 }
539
usb_dc_set_status_callback(const usb_dc_status_callback cb)540 void usb_dc_set_status_callback(const usb_dc_status_callback cb)
541 {
542 LOG_DBG("");
543
544 usb_dc_stm32_state.status_cb = cb;
545 }
546
usb_dc_set_address(const uint8_t addr)547 int usb_dc_set_address(const uint8_t addr)
548 {
549 HAL_StatusTypeDef status;
550
551 LOG_DBG("addr %u (0x%02x)", addr, addr);
552
553 status = HAL_PCD_SetAddress(&usb_dc_stm32_state.pcd, addr);
554 if (status != HAL_OK) {
555 LOG_ERR("HAL_PCD_SetAddress failed(0x%02x), %d", addr,
556 (int)status);
557 return -EIO;
558 }
559
560 return 0;
561 }
562
usb_dc_ep_start_read(uint8_t ep,uint8_t * data,uint32_t max_data_len)563 int usb_dc_ep_start_read(uint8_t ep, uint8_t *data, uint32_t max_data_len)
564 {
565 HAL_StatusTypeDef status;
566
567 LOG_DBG("ep 0x%02x, len %u", ep, max_data_len);
568
569 /* we flush EP0_IN by doing a 0 length receive on it */
570 if (!USB_EP_DIR_IS_OUT(ep) && (ep != EP0_IN || max_data_len)) {
571 LOG_ERR("invalid ep 0x%02x", ep);
572 return -EINVAL;
573 }
574
575 if (max_data_len > EP_MPS) {
576 max_data_len = EP_MPS;
577 }
578
579 status = HAL_PCD_EP_Receive(&usb_dc_stm32_state.pcd, ep,
580 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
581 max_data_len);
582 if (status != HAL_OK) {
583 LOG_ERR("HAL_PCD_EP_Receive failed(0x%02x), %d", ep,
584 (int)status);
585 return -EIO;
586 }
587
588 return 0;
589 }
590
usb_dc_ep_get_read_count(uint8_t ep,uint32_t * read_bytes)591 int usb_dc_ep_get_read_count(uint8_t ep, uint32_t *read_bytes)
592 {
593 if (!USB_EP_DIR_IS_OUT(ep) || !read_bytes) {
594 LOG_ERR("invalid ep 0x%02x", ep);
595 return -EINVAL;
596 }
597
598 *read_bytes = HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, ep);
599
600 return 0;
601 }
602
usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)603 int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg)
604 {
605 uint8_t ep_idx = USB_EP_GET_IDX(cfg->ep_addr);
606
607 LOG_DBG("ep %x, mps %d, type %d", cfg->ep_addr, cfg->ep_mps,
608 cfg->ep_type);
609
610 if ((cfg->ep_type == USB_DC_EP_CONTROL) && ep_idx) {
611 LOG_ERR("invalid endpoint configuration");
612 return -1;
613 }
614
615 if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
616 LOG_ERR("endpoint index/address out of range");
617 return -1;
618 }
619
620 return 0;
621 }
622
usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)623 int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg)
624 {
625 uint8_t ep = ep_cfg->ep_addr;
626 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
627
628 if (!ep_state) {
629 return -EINVAL;
630 }
631
632 LOG_DBG("ep 0x%02x, previous ep_mps %u, ep_mps %u, ep_type %u",
633 ep_cfg->ep_addr, ep_state->ep_mps, ep_cfg->ep_mps,
634 ep_cfg->ep_type);
635
636 #if defined(USB) || defined(USB_DRD_FS)
637 if (ep_cfg->ep_mps > ep_state->ep_pma_buf_len) {
638 if (USB_RAM_SIZE <=
639 (usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps)) {
640 return -EINVAL;
641 }
642 HAL_PCDEx_PMAConfig(&usb_dc_stm32_state.pcd, ep, PCD_SNG_BUF,
643 usb_dc_stm32_state.pma_offset);
644 ep_state->ep_pma_buf_len = ep_cfg->ep_mps;
645 usb_dc_stm32_state.pma_offset += ep_cfg->ep_mps;
646 }
647 #endif
648 ep_state->ep_mps = ep_cfg->ep_mps;
649
650 switch (ep_cfg->ep_type) {
651 case USB_DC_EP_CONTROL:
652 ep_state->ep_type = EP_TYPE_CTRL;
653 break;
654 case USB_DC_EP_ISOCHRONOUS:
655 ep_state->ep_type = EP_TYPE_ISOC;
656 break;
657 case USB_DC_EP_BULK:
658 ep_state->ep_type = EP_TYPE_BULK;
659 break;
660 case USB_DC_EP_INTERRUPT:
661 ep_state->ep_type = EP_TYPE_INTR;
662 break;
663 default:
664 return -EINVAL;
665 }
666
667 return 0;
668 }
669
usb_dc_ep_set_stall(const uint8_t ep)670 int usb_dc_ep_set_stall(const uint8_t ep)
671 {
672 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
673 HAL_StatusTypeDef status;
674
675 LOG_DBG("ep 0x%02x", ep);
676
677 if (!ep_state) {
678 return -EINVAL;
679 }
680
681 status = HAL_PCD_EP_SetStall(&usb_dc_stm32_state.pcd, ep);
682 if (status != HAL_OK) {
683 LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d", ep,
684 (int)status);
685 return -EIO;
686 }
687
688 ep_state->ep_stalled = 1U;
689
690 return 0;
691 }
692
usb_dc_ep_clear_stall(const uint8_t ep)693 int usb_dc_ep_clear_stall(const uint8_t ep)
694 {
695 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
696 HAL_StatusTypeDef status;
697
698 LOG_DBG("ep 0x%02x", ep);
699
700 if (!ep_state) {
701 return -EINVAL;
702 }
703
704 status = HAL_PCD_EP_ClrStall(&usb_dc_stm32_state.pcd, ep);
705 if (status != HAL_OK) {
706 LOG_ERR("HAL_PCD_EP_ClrStall failed(0x%02x), %d", ep,
707 (int)status);
708 return -EIO;
709 }
710
711 ep_state->ep_stalled = 0U;
712 ep_state->read_count = 0U;
713
714 return 0;
715 }
716
usb_dc_ep_is_stalled(const uint8_t ep,uint8_t * const stalled)717 int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled)
718 {
719 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
720
721 LOG_DBG("ep 0x%02x", ep);
722
723 if (!ep_state || !stalled) {
724 return -EINVAL;
725 }
726
727 *stalled = ep_state->ep_stalled;
728
729 return 0;
730 }
731
usb_dc_ep_enable(const uint8_t ep)732 int usb_dc_ep_enable(const uint8_t ep)
733 {
734 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
735 HAL_StatusTypeDef status;
736
737 LOG_DBG("ep 0x%02x", ep);
738
739 if (!ep_state) {
740 return -EINVAL;
741 }
742
743 LOG_DBG("HAL_PCD_EP_Open(0x%02x, %u, %u)", ep, ep_state->ep_mps,
744 ep_state->ep_type);
745
746 status = HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, ep,
747 ep_state->ep_mps, ep_state->ep_type);
748 if (status != HAL_OK) {
749 LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d", ep,
750 (int)status);
751 return -EIO;
752 }
753
754 if (USB_EP_DIR_IS_OUT(ep) && ep != EP0_OUT) {
755 return usb_dc_ep_start_read(ep,
756 usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
757 EP_MPS);
758 }
759
760 return 0;
761 }
762
usb_dc_ep_disable(const uint8_t ep)763 int usb_dc_ep_disable(const uint8_t ep)
764 {
765 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
766 HAL_StatusTypeDef status;
767
768 LOG_DBG("ep 0x%02x", ep);
769
770 if (!ep_state) {
771 return -EINVAL;
772 }
773
774 status = HAL_PCD_EP_Close(&usb_dc_stm32_state.pcd, ep);
775 if (status != HAL_OK) {
776 LOG_ERR("HAL_PCD_EP_Close failed(0x%02x), %d", ep,
777 (int)status);
778 return -EIO;
779 }
780
781 return 0;
782 }
783
usb_dc_ep_write(const uint8_t ep,const uint8_t * const data,const uint32_t data_len,uint32_t * const ret_bytes)784 int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data,
785 const uint32_t data_len, uint32_t * const ret_bytes)
786 {
787 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
788 HAL_StatusTypeDef status;
789 uint32_t len = data_len;
790 int ret = 0;
791
792 LOG_DBG("ep 0x%02x, len %u", ep, data_len);
793
794 if (!ep_state || !USB_EP_DIR_IS_IN(ep)) {
795 LOG_ERR("invalid ep 0x%02x", ep);
796 return -EINVAL;
797 }
798
799 ret = k_sem_take(&ep_state->write_sem, K_NO_WAIT);
800 if (ret) {
801 LOG_ERR("Unable to get write lock (%d)", ret);
802 return -EAGAIN;
803 }
804
805 if (!k_is_in_isr()) {
806 irq_disable(USB_IRQ);
807 }
808
809 if (ep == EP0_IN && len > USB_MAX_CTRL_MPS) {
810 len = USB_MAX_CTRL_MPS;
811 }
812
813 status = HAL_PCD_EP_Transmit(&usb_dc_stm32_state.pcd, ep,
814 (void *)data, len);
815 if (status != HAL_OK) {
816 LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep,
817 (int)status);
818 k_sem_give(&ep_state->write_sem);
819 ret = -EIO;
820 }
821
822 if (!ret && ep == EP0_IN && len > 0) {
823 /* Wait for an empty package as from the host.
824 * This also flushes the TX FIFO to the host.
825 */
826 usb_dc_ep_start_read(ep, NULL, 0);
827 }
828
829 if (!k_is_in_isr()) {
830 irq_enable(USB_IRQ);
831 }
832
833 if (!ret && ret_bytes) {
834 *ret_bytes = len;
835 }
836
837 return ret;
838 }
839
usb_dc_ep_read_wait(uint8_t ep,uint8_t * data,uint32_t max_data_len,uint32_t * read_bytes)840 int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len,
841 uint32_t *read_bytes)
842 {
843 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
844 uint32_t read_count;
845
846 if (!ep_state) {
847 LOG_ERR("Invalid Endpoint %x", ep);
848 return -EINVAL;
849 }
850
851 read_count = ep_state->read_count;
852
853 LOG_DBG("ep 0x%02x, %u bytes, %u+%u, %p", ep, max_data_len,
854 ep_state->read_offset, read_count, data);
855
856 if (!USB_EP_DIR_IS_OUT(ep)) { /* check if OUT ep */
857 LOG_ERR("Wrong endpoint direction: 0x%02x", ep);
858 return -EINVAL;
859 }
860
861 /* When both buffer and max data to read are zero, just ingore reading
862 * and return available data in buffer. Otherwise, return data
863 * previously stored in the buffer.
864 */
865 if (data) {
866 read_count = MIN(read_count, max_data_len);
867 memcpy(data, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)] +
868 ep_state->read_offset, read_count);
869 ep_state->read_count -= read_count;
870 ep_state->read_offset += read_count;
871 } else if (max_data_len) {
872 LOG_ERR("Wrong arguments");
873 }
874
875 if (read_bytes) {
876 *read_bytes = read_count;
877 }
878
879 return 0;
880 }
881
usb_dc_ep_read_continue(uint8_t ep)882 int usb_dc_ep_read_continue(uint8_t ep)
883 {
884 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
885
886 if (!ep_state || !USB_EP_DIR_IS_OUT(ep)) { /* Check if OUT ep */
887 LOG_ERR("Not valid endpoint: %02x", ep);
888 return -EINVAL;
889 }
890
891 /* If no more data in the buffer, start a new read transaction.
892 * DataOutStageCallback will called on transaction complete.
893 */
894 if (!ep_state->read_count) {
895 usb_dc_ep_start_read(ep, usb_dc_stm32_state.ep_buf[USB_EP_GET_IDX(ep)],
896 EP_MPS);
897 }
898
899 return 0;
900 }
901
usb_dc_ep_read(const uint8_t ep,uint8_t * const data,const uint32_t max_data_len,uint32_t * const read_bytes)902 int usb_dc_ep_read(const uint8_t ep, uint8_t *const data, const uint32_t max_data_len,
903 uint32_t * const read_bytes)
904 {
905 if (usb_dc_ep_read_wait(ep, data, max_data_len, read_bytes) != 0) {
906 return -EINVAL;
907 }
908
909 if (usb_dc_ep_read_continue(ep) != 0) {
910 return -EINVAL;
911 }
912
913 return 0;
914 }
915
usb_dc_ep_halt(const uint8_t ep)916 int usb_dc_ep_halt(const uint8_t ep)
917 {
918 return usb_dc_ep_set_stall(ep);
919 }
920
usb_dc_ep_flush(const uint8_t ep)921 int usb_dc_ep_flush(const uint8_t ep)
922 {
923 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
924
925 if (!ep_state) {
926 return -EINVAL;
927 }
928
929 LOG_ERR("Not implemented");
930
931 return 0;
932 }
933
usb_dc_ep_mps(const uint8_t ep)934 int usb_dc_ep_mps(const uint8_t ep)
935 {
936 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
937
938 if (!ep_state) {
939 return -EINVAL;
940 }
941
942 return ep_state->ep_mps;
943 }
944
usb_dc_detach(void)945 int usb_dc_detach(void)
946 {
947 LOG_ERR("Not implemented");
948
949 #ifdef CONFIG_SOC_SERIES_STM32WBX
950 /* Specially for STM32WB, unlock the HSEM when USB is no more used. */
951 z_stm32_hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);
952
953 /*
954 * TODO: AN5289 notes a process of locking Sem0, with possible waits
955 * via interrupts before switching off CLK48, but lacking any actual
956 * examples of that, that remains to be implemented. See
957 * https://github.com/zephyrproject-rtos/zephyr/pull/25850
958 */
959 #endif /* CONFIG_SOC_SERIES_STM32WBX */
960
961 return 0;
962 }
963
usb_dc_reset(void)964 int usb_dc_reset(void)
965 {
966 LOG_ERR("Not implemented");
967
968 return 0;
969 }
970
971 /* Callbacks from the STM32 Cube HAL code */
972
HAL_PCD_ResetCallback(PCD_HandleTypeDef * hpcd)973 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
974 {
975 int i;
976
977 LOG_DBG("");
978
979 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_IN, EP0_MPS, EP_TYPE_CTRL);
980 HAL_PCD_EP_Open(&usb_dc_stm32_state.pcd, EP0_OUT, EP0_MPS,
981 EP_TYPE_CTRL);
982
983 /* The DataInCallback will never be called at this point for any pending
984 * transactions. Reset the IN semaphores to prevent perpetual locked state.
985 * */
986 for (i = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
987 k_sem_give(&usb_dc_stm32_state.in_ep_state[i].write_sem);
988 }
989
990 if (usb_dc_stm32_state.status_cb) {
991 usb_dc_stm32_state.status_cb(USB_DC_RESET, NULL);
992 }
993 }
994
HAL_PCD_ConnectCallback(PCD_HandleTypeDef * hpcd)995 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
996 {
997 LOG_DBG("");
998
999 if (usb_dc_stm32_state.status_cb) {
1000 usb_dc_stm32_state.status_cb(USB_DC_CONNECTED, NULL);
1001 }
1002 }
1003
HAL_PCD_DisconnectCallback(PCD_HandleTypeDef * hpcd)1004 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
1005 {
1006 LOG_DBG("");
1007
1008 if (usb_dc_stm32_state.status_cb) {
1009 usb_dc_stm32_state.status_cb(USB_DC_DISCONNECTED, NULL);
1010 }
1011 }
1012
HAL_PCD_SuspendCallback(PCD_HandleTypeDef * hpcd)1013 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
1014 {
1015 LOG_DBG("");
1016
1017 if (usb_dc_stm32_state.status_cb) {
1018 usb_dc_stm32_state.status_cb(USB_DC_SUSPEND, NULL);
1019 }
1020 }
1021
HAL_PCD_ResumeCallback(PCD_HandleTypeDef * hpcd)1022 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
1023 {
1024 LOG_DBG("");
1025
1026 if (usb_dc_stm32_state.status_cb) {
1027 usb_dc_stm32_state.status_cb(USB_DC_RESUME, NULL);
1028 }
1029 }
1030
HAL_PCD_SetupStageCallback(PCD_HandleTypeDef * hpcd)1031 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
1032 {
1033 struct usb_setup_packet *setup = (void *)usb_dc_stm32_state.pcd.Setup;
1034 struct usb_dc_stm32_ep_state *ep_state;
1035
1036 LOG_DBG("");
1037
1038 ep_state = usb_dc_stm32_get_ep_state(EP0_OUT); /* can't fail for ep0 */
1039 __ASSERT(ep_state, "No corresponding ep_state for EP0");
1040
1041 ep_state->read_count = SETUP_SIZE;
1042 ep_state->read_offset = 0U;
1043 memcpy(&usb_dc_stm32_state.ep_buf[EP0_IDX],
1044 usb_dc_stm32_state.pcd.Setup, ep_state->read_count);
1045
1046 if (ep_state->cb) {
1047 ep_state->cb(EP0_OUT, USB_DC_EP_SETUP);
1048
1049 if (!(setup->wLength == 0U) &&
1050 usb_reqtype_is_to_device(setup)) {
1051 usb_dc_ep_start_read(EP0_OUT,
1052 usb_dc_stm32_state.ep_buf[EP0_IDX],
1053 setup->wLength);
1054 }
1055 }
1056 }
1057
HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1058 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1059 {
1060 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1061 uint8_t ep = ep_idx | USB_EP_DIR_OUT;
1062 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1063
1064 LOG_DBG("epnum 0x%02x, rx_count %u", epnum,
1065 HAL_PCD_EP_GetRxCount(&usb_dc_stm32_state.pcd, epnum));
1066
1067 /* Transaction complete, data is now stored in the buffer and ready
1068 * for the upper stack (usb_dc_ep_read to retrieve).
1069 */
1070 usb_dc_ep_get_read_count(ep, &ep_state->read_count);
1071 ep_state->read_offset = 0U;
1072
1073 if (ep_state->cb) {
1074 ep_state->cb(ep, USB_DC_EP_DATA_OUT);
1075 }
1076 }
1077
HAL_PCD_DataInStageCallback(PCD_HandleTypeDef * hpcd,uint8_t epnum)1078 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
1079 {
1080 uint8_t ep_idx = USB_EP_GET_IDX(epnum);
1081 uint8_t ep = ep_idx | USB_EP_DIR_IN;
1082 struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
1083
1084 LOG_DBG("epnum 0x%02x", epnum);
1085
1086 __ASSERT(ep_state, "No corresponding ep_state for ep");
1087
1088 k_sem_give(&ep_state->write_sem);
1089
1090 if (ep_state->cb) {
1091 ep_state->cb(ep, USB_DC_EP_DATA_IN);
1092 }
1093 }
1094
1095 #if (defined(USB) || defined(USB_DRD_FS)) && defined(CONFIG_USB_DC_STM32_DISCONN_ENABLE)
HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef * hpcd,uint8_t state)1096 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
1097 {
1098 const struct device *usb_disconnect;
1099
1100 usb_disconnect = device_get_binding(
1101 DT_GPIO_LABEL(DT_INST(0, st_stm32_usb), disconnect_gpios));
1102
1103 gpio_pin_configure(usb_disconnect,
1104 DT_GPIO_PIN(DT_INST(0, st_stm32_usb), disconnect_gpios),
1105 DT_GPIO_FLAGS(DT_INST(0, st_stm32_usb), disconnect_gpios) |
1106 (state ? GPIO_OUTPUT_ACTIVE : GPIO_OUTPUT_INACTIVE));
1107 }
1108 #endif /* USB && CONFIG_USB_DC_STM32_DISCONN_ENABLE */
1109
