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Searched refs:DT_REG_SIZE (Results 1 – 25 of 60) sorted by relevance

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/Zephyr-Core-2.7.6/boards/arc/em_starterkit/
Darc_mpu_regions.c17 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
21 DT_REG_SIZE(DT_INST(0, arc_iccm)),
24 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
28 DT_REG_SIZE(DT_INST(0, arc_dccm)),
32 #if DT_REG_SIZE(DT_INST(0, mmio_sram)) > 0
36 DT_REG_SIZE(DT_INST(0, mmio_sram)),
/Zephyr-Core-2.7.6/soc/arc/snps_arc_iot/
Dlinker.ld19 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
21 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
25 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
27 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
32 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
34 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
41 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
43 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-2.7.6/soc/arc/snps_emsdp/
Dlinker.ld19 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
21 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
27 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
29 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
37 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
39 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-2.7.6/boards/arc/qemu_arc/
Darc_mpu_regions.c26 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
30 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
34 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
38 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
/Zephyr-Core-2.7.6/boards/arc/nsim/
Darc_mpu_regions.c26 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
30 DT_REG_SIZE(DT_INST(0, arc_iccm)),
33 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
37 DT_REG_SIZE(DT_INST(0, arc_dccm)),
/Zephyr-Core-2.7.6/soc/arc/snps_emsk/
Dlinker.ld21 (DT_REG_SIZE(DT_NODELABEL(ddr0)) > 0)
23 #define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(ddr0))
28 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
30 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
38 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
40 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-2.7.6/soc/arc/snps_qemu/
Dlinker.ld14 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
16 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
23 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
25 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-2.7.6/soc/arm/nxp_imx/rt/
Dlinker.ld14 #if (DT_REG_SIZE(DT_NODELABEL(ocram)) > 0) && !IS_CHOSEN_SRAM(ocram)
15 … OCRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ocram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ocram))
17 #if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
18 …SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0…
/Zephyr-Core-2.7.6/boards/arc/emsdp/
Darc_mpu_regions.c16 DT_REG_SIZE(DT_INST(0, arc_iccm)),
21 DT_REG_SIZE(DT_INST(0, arc_dccm)),
26 DT_REG_SIZE(DT_INST(0, mmio_sram)),
/Zephyr-Core-2.7.6/soc/arc/snps_nsim/
Dlinker.ld16 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
18 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
26 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
28 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-Core-2.7.6/tests/drivers/syscon/src/
Dmain.c10 uint8_t var_in_res0[DT_REG_SIZE(DT_NODELABEL(syscon))] __attribute((__section__(".res0")));
15 const size_t expected_size = DT_REG_SIZE(DT_NODELABEL(syscon)); in test_size()
29 zassert_equal(syscon_read_reg(dev, DT_REG_SIZE(DT_NODELABEL(syscon)), &val), -EINVAL, NULL); in test_out_of_bounds()
30 zassert_equal(syscon_write_reg(dev, DT_REG_SIZE(DT_NODELABEL(syscon)), val), -EINVAL, NULL); in test_out_of_bounds()
/Zephyr-Core-2.7.6/include/linker/
Ddevicetree_reserved.h25 LENGTH = DT_REG_SIZE(res)
34 _DT_RESERVED_START(res) + DT_REG_SIZE(res); \
103 #define LINKER_DT_RESERVED_MEM_GET_SIZE(node_id) DT_REG_SIZE(node_id)
Ddevicetree_regions.h13 LENGTH = DT_REG_SIZE(node)
/Zephyr-Core-2.7.6/boards/arc/iotdk/
Darc_mpu_regions.c16 DT_REG_SIZE(DT_INST(0, arc_iccm)),
21 DT_REG_SIZE(DT_INST(0, arc_dccm)),
/Zephyr-Core-2.7.6/soc/nios2/nios2f-zephyr/
Dlinker.ld15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-2.7.6/soc/nios2/nios2-qemu/
Dlinker.ld15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-2.7.6/soc/arc/snps_arc_hsdk/
Dlinker.ld18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-Core-2.7.6/soc/xtensa/intel_s1000/
Dmemory.h15 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
73 #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/Zephyr-Core-2.7.6/soc/riscv/riscv-privilege/telink_b91/
Dlinker.ld17 …ROM_INIT (rx) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_flash)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zep…
18 …RAM_ILM (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ra…
/Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v15/include/soc/
Dmemory.h18 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
208 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v18/include/soc/
Dmemory.h15 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
210 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v20/include/soc/
Dmemory.h15 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
210 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/Zephyr-Core-2.7.6/subsys/storage/flash_map/
Dflash_map_default.c17 .fa_size = DT_REG_SIZE(part),},
/Zephyr-Core-2.7.6/arch/x86/core/
Dmemmap.c41 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
/Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v25/include/soc/
Dmemory.h15 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
210 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))

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