1 /*
2  * Copyright (c) 2019 Intel Corporation
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef __INC_SOC_H
7 #define __INC_SOC_H
8 
9 #include <arch/xtensa/cache.h>
10 
11 /* macros related to interrupt handling */
12 #define XTENSA_IRQ_NUM_SHIFT			0
13 #define CAVS_IRQ_NUM_SHIFT			8
14 #define INTR_CNTL_IRQ_NUM_SHIFT			16
15 #define XTENSA_IRQ_NUM_MASK			0xff
16 #define CAVS_IRQ_NUM_MASK			0xff
17 #define INTR_CNTL_IRQ_NUM_MASK			0xff
18 
19 /*
20  * IRQs are mapped on 3 levels. 4th level is left 0x00.
21  *
22  * 1. Peripheral Register bit offset.
23  * 2. CAVS logic bit offset.
24  * 3. Core interrupt number.
25  */
26 #define XTENSA_IRQ_NUMBER(_irq) \
27 	((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
28 #define CAVS_IRQ_NUMBER(_irq) \
29 	(((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1)
30 #define INTR_CNTL_IRQ_NUM(_irq) \
31 	(((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1)
32 
33 /* Macro that aggregates the tri-level interrupt into an IRQ number */
34 #define SOC_AGGREGATE_IRQ(ictl_irq, cavs_irq, core_irq)		\
35 	(((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) |	\
36 	(((cavs_irq) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) |	\
37 	(((ictl_irq) & INTR_CNTL_IRQ_NUM_MASK) << INTR_CNTL_IRQ_NUM_SHIFT))
38 
39 #define CAVS_L2_AGG_INT_LEVEL2			DT_IRQN(DT_INST(0, intel_cavs_intc))
40 #define CAVS_L2_AGG_INT_LEVEL3			DT_IRQN(DT_INST(1, intel_cavs_intc))
41 #define CAVS_L2_AGG_INT_LEVEL4			DT_IRQN(DT_INST(2, intel_cavs_intc))
42 #define CAVS_L2_AGG_INT_LEVEL5			DT_IRQN(DT_INST(3, intel_cavs_intc))
43 
44 #define CAVS_ICTL_INT_CPU_OFFSET(x)		(0x40 * x)
45 
46 #define IOAPIC_EDGE				0
47 #define IOAPIC_HIGH				0
48 
49 /* DW interrupt controller */
50 #define DW_ICTL_IRQ_CAVS_OFFSET			CAVS_IRQ_NUMBER(DT_IRQN(DT_INST(0, snps_designware_intc)))
51 #define DW_ICTL_NUM_IRQS			9
52 
53 /* GPIO */
54 #define GPIO_DW_PORT_0_INT_MASK			0
55 
56 #define DMA_HANDSHAKE_DMIC_RXA			0
57 #define DMA_HANDSHAKE_DMIC_RXB			1
58 #define DMA_HANDSHAKE_SSP0_TX			2
59 #define DMA_HANDSHAKE_SSP0_RX			3
60 #define DMA_HANDSHAKE_SSP1_TX			4
61 #define DMA_HANDSHAKE_SSP1_RX			5
62 #define DMA_HANDSHAKE_SSP2_TX			6
63 #define DMA_HANDSHAKE_SSP2_RX			7
64 #define DMA_HANDSHAKE_SSP3_TX			8
65 #define DMA_HANDSHAKE_SSP3_RX			9
66 
67 /* I2S */
68 #define I2S_CAVS_IRQ(i2s_num)			\
69 	SOC_AGGREGATE_IRQ(0, (i2s_num) + 1, CAVS_L2_AGG_INT_LEVEL5)
70 
71 #define I2S0_CAVS_IRQ				I2S_CAVS_IRQ(0)
72 #define I2S1_CAVS_IRQ				I2S_CAVS_IRQ(1)
73 #define I2S2_CAVS_IRQ				I2S_CAVS_IRQ(2)
74 #define I2S3_CAVS_IRQ				I2S_CAVS_IRQ(3)
75 
76 #define SSP_SIZE				0x0000200
77 #define SSP_BASE(x)				(0x00077000 + (x) * SSP_SIZE)
78 #define SSP_MN_DIV_SIZE				(8)
79 #define SSP_MN_DIV_BASE(x)			\
80 	(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
81 
82 /* MCLK control */
83 #define SOC_MCLK_DIV_CTRL_BASE			0x78C00
84 #define SOC_NUM_MCLK_OUTPUTS			2
85 #define SOC_MDIVCTRL_MCLK_OUT_EN(mclk)		BIT(mclk)
86 #define SOC_MDIVXR_SET_DIVIDER_BYPASS		BIT_MASK(12)
87 
88 struct soc_mclk_control_regs {
89 	uint32_t	mdivctrl;
90 	uint32_t	reserved[31];
91 	uint32_t	mdivxr[SOC_NUM_MCLK_OUTPUTS];
92 };
93 
94 #define PDM_BASE				0x00010000
95 
96 #define SOC_NUM_LPGPDMAC			3
97 #define SOC_NUM_CHANNELS_IN_DMAC		8
98 
99 /* DSP Wall Clock Timers (0 and 1) */
100 #define DSP_WCT_IRQ(x)	\
101 	SOC_AGGREGATE_IRQ(0, (23 + x), CAVS_L2_AGG_INT_LEVEL2)
102 
103 #define DSP_WCT_CS_TA(x)			BIT(x)
104 #define DSP_WCT_CS_TT(x)			BIT(4 + x)
105 
106 /* SOC Resource Allocation Registers */
107 #define SOC_RESOURCE_ALLOC_REG_BASE		0x00071A60
108 /* bit field definition for LP GPDMA ownership register */
109 #define SOC_LPGPDMAC_OWNER_DSP			\
110 	(BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC))
111 
112 #define SOC_NUM_I2S_INSTANCES			4
113 /* bit field definition for IO peripheral ownership register */
114 #define SOC_DSPIOP_I2S_OWNSEL_DSP		\
115 	(BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8)
116 #define SOC_DSPIOP_DMIC_OWNSEL_DSP		BIT(0)
117 
118 /* bit field definition for general ownership register */
119 #define SOC_GENO_TIMESTAMP_OWNER_DSP		BIT(2)
120 #define SOC_GENO_MNDIV_OWNER_DSP		BIT(1)
121 
122 struct soc_resource_alloc_regs {
123 	union {
124 		uint16_t	lpgpdmacxo[SOC_NUM_LPGPDMAC];
125 		uint16_t	reserved[4];
126 	};
127 	uint32_t	dspiopo;
128 	uint32_t	geno;
129 };
130 
131 /* L2 Local Memory Registers */
132 #define SOC_L2RAM_LOCAL_MEM_REG_BASE		0x00071D00
133 #define SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL		\
134 	(SOC_L2RAM_LOCAL_MEM_REG_BASE + 0x50)
135 
136 /* DMIC SHIM Registers */
137 #define SOC_DMIC_SHIM_REG_BASE			0x00071E80
138 #define SOC_DMIC_SHIM_DMICLCTL_SPA		BIT(0)
139 #define SOC_DMIC_SHIM_DMICLCTL_CPA		BIT(8)
140 
141 struct soc_dmic_shim_regs {
142 	uint32_t	dmiclcap;
143 	uint32_t	dmiclctl;
144 };
145 
146 /* SOC DSP SHIM Registers */
147 #define SOC_DSP_SHIM_REG_BASE			0x00071F00
148 /* SOC DSP SHIM Register - Clock Control */
149 #define SOC_CLKCTL_REQ_FAST_CLK			BIT(31)
150 #define SOC_CLKCTL_REQ_SLOW_CLK			BIT(30)
151 #define SOC_CLKCTL_OCS_FAST_CLK			BIT(2)
152 /* SOC DSP SHIM Register - Power Control */
153 #define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0	BIT(0)
154 #define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1	BIT(1)
155 
156 struct soc_dsp_shim_regs {
157 	uint32_t	reserved[8];
158 	union {
159 		struct {
160 			uint32_t walclk32_lo;
161 			uint32_t walclk32_hi;
162 		};
163 		uint64_t	walclk;
164 	};
165 	uint32_t	dspwctcs;
166 	uint32_t	reserved1[1];
167 	union {
168 		struct {
169 			uint32_t dspwct0c32_lo;
170 			uint32_t dspwct0c32_hi;
171 		};
172 		uint64_t	dspwct0c;
173 	};
174 	union {
175 		struct {
176 			uint32_t dspwct1c32_lo;
177 			uint32_t dspwct1c32_hi;
178 		};
179 		uint64_t	dspwct1c;
180 	};
181 	uint32_t	reserved2[14];
182 	uint32_t	clkctl;
183 	uint32_t	clksts;
184 	uint32_t	reserved3[4];
185 	uint16_t	pwrctl;
186 	uint16_t	pwrsts;
187 	uint32_t	lpsctl;
188 	uint32_t	lpsdmas0;
189 	uint32_t	lpsdmas1;
190 	uint32_t	reserved4[22];
191 };
192 
193 /* Global Control registers */
194 #define SOC_S1000_GLB_CTRL_BASE			(0x00081C00)
195 
196 #define SOC_GNA_POWER_CONTROL_SPA		(BIT(0))
197 #define SOC_GNA_POWER_CONTROL_CPA		(BIT(8))
198 #define SOC_GNA_POWER_CONTROL_CLK_EN		(BIT(16))
199 
200 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST	BIT(1)
201 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL	BIT(9)
202 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA	BIT(17)
203 #define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA	BIT(25)
204 
205 #define SOC_S1000_STRAP_REF_CLK			(BIT_MASK(2) << 3)
206 #define SOC_S1000_STRAP_REF_CLK_38P4		(0 << 3)
207 #define SOC_S1000_STRAP_REF_CLK_19P2		(1 << 3)
208 #define SOC_S1000_STRAP_REF_CLK_24P576		(2 << 3)
209 
210 struct soc_global_regs {
211 	uint32_t	reserved1[5];
212 	uint32_t	cavs_dsp1power_control;
213 	uint32_t	reserved2[2];
214 	uint32_t	gna_power_control;
215 	uint32_t	reserved3[7];
216 	uint32_t	straps;
217 };
218 
219 /* macros for data cache operations */
220 #define SOC_DCACHE_FLUSH(addr, size)		\
221 	z_xtensa_cache_flush((addr), (size))
222 #define SOC_DCACHE_INVALIDATE(addr, size)	\
223 	z_xtensa_cache_inv((addr), (size))
224 
225 extern void z_soc_irq_enable(uint32_t irq);
226 extern void z_soc_irq_disable(uint32_t irq);
227 extern int z_soc_irq_is_enabled(unsigned int irq);
228 
229 extern uint32_t soc_get_ref_clk_freq(void);
230 
231 #endif /* __INC_SOC_H */
232