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/Zephyr-4.3.0/lib/libc/minimal/source/math/
Dsqrt.c27 int64double_t root; in sqrt() local
50 root.i = (p_square.i & ~EXP_MASK64) | (exponent + 1023) << 52; in sqrt()
53 last = root; in sqrt()
54 root.d = (root.d + square / root.d) * 0.5; in sqrt()
56 if ((root.i ^ last.i) < MAX_D_ERROR_COUNT) { in sqrt()
60 return root.d; in sqrt()
Dsqrtf.c27 intfloat_t root; in sqrtf() local
50 root.i = (p_square.i & ~EXP_MASK32) | (exponent + 127) << 23; in sqrtf()
53 last = root; in sqrtf()
54 root.f = (root.f + square / root.f) * 0.5f; in sqrtf()
56 if ((root.i ^ last.i) < MAX_F_ERROR_COUNT) { in sqrtf()
60 return root.f; in sqrtf()
/Zephyr-4.3.0/soc/nxp/imx/imx7d/
Dsoc_clk_freq.c14 uint32_t root; in get_pwm_clock_freq() local
20 root = CCM_GetRootMux(CCM, ccmRootPwm1); in get_pwm_clock_freq()
24 root = CCM_GetRootMux(CCM, ccmRootPwm2); in get_pwm_clock_freq()
28 root = CCM_GetRootMux(CCM, ccmRootPwm3); in get_pwm_clock_freq()
32 root = CCM_GetRootMux(CCM, ccmRootPwm4); in get_pwm_clock_freq()
39 switch (root) { in get_pwm_clock_freq()
/Zephyr-4.3.0/tests/subsys/fs/common/
Dtest_fs_dirops.c148 struct testfs_path root; in check_rename() local
184 zassert_equal(testfs_path_init(&root, mp, in check_rename()
187 root.path, in check_rename()
190 zassert_equal(fs_mkdir(root.path), in check_rename()
193 zassert_equal(testfs_build(&root, from_bcmd), in check_rename()
197 zassert_equal(testfs_bcmd_verify_layout(&root, from_bcmd, from_end_bcmd), in check_rename()
201 testfs_path_extend(testfs_path_copy(&from_path, &root), in check_rename()
204 testfs_path_extend(testfs_path_copy(&to_path, &root), in check_rename()
213 testfs_path_extend(testfs_path_copy(&from_path, &root), in check_rename()
222 testfs_path_extend(testfs_path_copy(&from_path, &root), in check_rename()
[all …]
/Zephyr-4.3.0/soc/nxp/imx/imx6sx/
Dsoc_clk_freq.c15 uint32_t root; in get_pwm_clock_freq() local
23 root = ccmRootmuxPerclkClkOsc24m; in get_pwm_clock_freq()
31 root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel); in get_pwm_clock_freq()
36 switch (root) { in get_pwm_clock_freq()
49 root = ccmRootmuxPeriphClk2OSC24m; in get_pwm_clock_freq()
56 root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel); in get_pwm_clock_freq()
61 switch (root) { in get_pwm_clock_freq()
/Zephyr-4.3.0/lib/libc/minimal/source/stdlib/
Dqsort.c54 int root; in sift_down() local
58 for (swap = start, root = swap; left(root) < end; root = swap) { in sift_down()
59 child = left(root); in sift_down()
67 if (right(root) < end && compare(cmp, A(swap), A(right(root))) < 0) { in sift_down()
68 swap = right(root); in sift_down()
71 if (swap == root) { in sift_down()
75 byteswp(A(root), A(swap), size); in sift_down()
/Zephyr-4.3.0/subsys/usb/host/
Dusbh_core.c51 if (ctx->root != NULL) { in dev_connected_handler()
53 usbh_device_free(ctx->root); in dev_connected_handler()
54 ctx->root = NULL; in dev_connected_handler()
57 ctx->root = usbh_device_alloc(ctx); in dev_connected_handler()
58 if (ctx->root == NULL) { in dev_connected_handler()
63 ctx->root->state = USB_STATE_DEFAULT; in dev_connected_handler()
66 ctx->root->speed = USB_SPEED_SPEED_HS; in dev_connected_handler()
68 ctx->root->speed = USB_SPEED_SPEED_FS; in dev_connected_handler()
71 if (usbh_device_init(ctx->root)) { in dev_connected_handler()
78 if (ctx->root != NULL) { in dev_removed_handler()
[all …]
/Zephyr-4.3.0/tests/benchmarks/data_structure_perf/rbtree_perf/src/
Drbtree_perf.c134 static void verify_rbtree_perf(struct rbnode *root, struct rbnode *test) in verify_rbtree_perf() argument
138 node_height = search_height_recurse(root, test, node_height); in verify_rbtree_perf()
192 struct rbnode *root = test_rbtree.root; in ZTEST() local
196 verify_rbtree_perf(root, test); in ZTEST()
199 verify_rbtree_perf(root, test); in ZTEST()
207 verify_rbtree_perf(root, test); in ZTEST()
/Zephyr-4.3.0/drivers/clock_control/
DKconfig.renesas_rx_cgc14 bool "Renesas RX root clock source"
17 Enable Renesas RX root clock
20 bool "Renesas RX root clock source"
26 bool "Renesas RX root clock source"
Dclock_control_bl70x.c64 struct clock_control_bl70x_root_config root; member
408 clock_control_bl70x_select_DLL(data->root.dll_select); in clock_control_bl70x_init_root_as_dll()
457 ret = clock_control_bl70x_set_root_clock_dividers(data->root.divider - 1, in clock_control_bl70x_update_root()
463 if (data->root.source == bl70x_clkid_clk_dll) { in clock_control_bl70x_update_root()
465 } else if (data->root.source == bl70x_clkid_clk_crystal) { in clock_control_bl70x_update_root()
579 if (data->root.source == bl70x_clkid_clk_rc32m) { in clock_control_bl70x_on()
583 data->root.source = bl70x_clkid_clk_rc32m; in clock_control_bl70x_on()
587 if (data->root.source == bl70x_clkid_clk_crystal) { in clock_control_bl70x_on()
590 oldroot = data->root.source; in clock_control_bl70x_on()
591 data->root.source = bl70x_clkid_clk_crystal; in clock_control_bl70x_on()
[all …]
Dclock_control_bl60x.c76 struct clock_control_bl60x_root_config root; member
525 clock_control_bl60x_select_PLL(data->root.pll_select); in clock_control_bl60x_init_root_as_pll()
577 ret = clock_control_bl60x_set_root_clock_dividers(data->root.divider - 1, in clock_control_bl60x_update_root()
583 if (data->root.source == bl60x_clkid_clk_pll) { in clock_control_bl60x_update_root()
585 } else if (data->root.source == bl60x_clkid_clk_crystal) { in clock_control_bl60x_update_root()
699 if (data->root.source == bl60x_clkid_clk_rc32m) { in clock_control_bl60x_on()
703 data->root.source = bl60x_clkid_clk_rc32m; in clock_control_bl60x_on()
707 if (data->root.source == bl60x_clkid_clk_crystal) { in clock_control_bl60x_on()
710 oldroot = data->root.source; in clock_control_bl60x_on()
711 data->root.source = bl60x_clkid_clk_crystal; in clock_control_bl60x_on()
[all …]
Dclock_control_bl61x.c90 struct clock_control_bl61x_root_config root; member
851 clock_control_bl61x_select_PLL(data->root.pll_select); in clock_control_bl61x_init_root_as_wifipll()
855 if (data->root.pll_select == 1) { in clock_control_bl61x_init_root_as_wifipll()
857 } else if (data->root.pll_select == 2) { in clock_control_bl61x_init_root_as_wifipll()
950 ret = clock_bflb_set_root_clock_dividers(data->root.divider - 1, data->bclk.divider - 1); in clock_control_bl61x_update_root()
955 if (data->root.source == bl61x_clkid_clk_wifipll) { in clock_control_bl61x_update_root()
957 } else if (data->root.source == bl61x_clkid_clk_crystal) { in clock_control_bl61x_update_root()
1086 if (data->root.source == bl61x_clkid_clk_rc32m) { in clock_control_bl61x_on()
1090 data->root.source = bl61x_clkid_clk_rc32m; in clock_control_bl61x_on()
1094 if (data->root.source == bl61x_clkid_clk_crystal) { in clock_control_bl61x_on()
[all …]
/Zephyr-4.3.0/scripts/dts/
Dgen_driver_kconfig_dts.py40 for root, _, filenames in os.walk(bindings_dir):
43 yield os.path.join(root, filename)
69 root = yaml.compose(f, Loader=SafeLoader)
75 if not isinstance(root, yaml.MappingNode):
77 for key, node in root.value:
/Zephyr-4.3.0/soc/
DCMakeLists.txt30 # Include all SoC roots except Zephyr, as we are already in the Zephyr SoC root.
33 foreach(root ${local_soc_root})
34 cmake_path(GET root FILENAME name)
35 # A SoC root for HWMv1 may not contain a CMakeLists.txt file on this so
37 if(EXISTS ${root}/soc/CMakeLists.txt)
38 add_subdirectory(${root}/soc soc/${name})
/Zephyr-4.3.0/subsys/fs/
Dfs_impl.c14 static const char *const root = "/"; in fs_impl_strip_prefix() local
21 return *path ? path : root; in fs_impl_strip_prefix()
/Zephyr-4.3.0/soc/nxp/imxrt/imxrt11xx/
Dflexspi.c16 clock_name_t root; in flexspi_clock_set_freq() local
37 root = CLOCK_GetRootClockSource(flexspi_clk, in flexspi_clock_set_freq()
40 root_rate = CLOCK_GetFreq(root); in flexspi_clock_set_freq()
/Zephyr-4.3.0/soc/nxp/imxrt/imxrt118x/
Dflexspi.c16 clock_name_t root; in flexspi_clock_set_freq() local
37 root = CLOCK_GetRootClockSource(flexspi_clk, in flexspi_clock_set_freq()
40 root_rate = CLOCK_GetFreq(root); in flexspi_clock_set_freq()
/Zephyr-4.3.0/doc/develop/application/
Dapplication-kconfig.include7 # Sources Kconfig.zephyr in the Zephyr root directory.
9 # Note: All 'source' statements work relative to the Zephyr root directory (due
12 # path relative to the Zephyr root).
/Zephyr-4.3.0/scripts/footprint/
Dupload_data.py67 root = importer.import_(contents['symbols'])
69 zr = find(root, lambda node: node.name == 'ZEPHYR_BASE')
70 ws = find(root, lambda node: node.name == 'WORKSPACE')
76 trees = [root]
78 for node in PreOrderIter(root, maxlevel=2):
86 root = t.name
88 if node.name == root:
/Zephyr-4.3.0/drivers/i2c/
Di2c_tca954x.c30 const struct device *root; member
40 return channel_config->root->data; in get_root_data_from_channel()
48 return channel_config->root->config; in get_root_config_from_channel()
93 res = tca954x_set_channel(down_cfg->root, down_cfg->chan_mask); in tca954x_transfer()
102 disconnect_res = tca954x_set_channel(down_cfg->root, 0); in tca954x_transfer()
151 if (!device_is_ready(chan_cfg->root)) { in tca954x_channel_init()
152 LOG_ERR("I2C mux root %s not ready", chan_cfg->root->name); in tca954x_channel_init()
181 .root = DEVICE_DT_GET(DT_PARENT(node_id)), \
/Zephyr-4.3.0/scripts/dts/python-devicetree/tests/
Dtest_dtlib.py843 phandle = dtlib.to_num(dt.root.props[prop].value[offset:offset + 4])
1593 actual = dt.root.props[prop].type
1699 actual = dt.root.props[prop].to_num(signed)
1705 dt.root.props[prop].to_num()
1737 actual = dt.root.props[prop].to_nums(signed)
1743 dt.root.props[prop].to_nums()
1767 actual = dt.root.props[prop].to_bytes()
1772 dt.root.props[prop].to_bytes()
1790 actual = dt.root.props[prop].to_string()
1795 dt.root.props[prop].to_string()
[all …]
/Zephyr-4.3.0/soc/nxp/imx/imx9/imx93/
Dcommon_clock_set.c18 clock_name_t root; in common_clock_set_freq() local
63 root = CLOCK_GetRootClockSource(clk_root, CLOCK_GetRootClockMux(clk_root)); in common_clock_set_freq()
64 root_rate = g_clockSourceFreq[root]; in common_clock_set_freq()
/Zephyr-4.3.0/cmake/modules/
DFindScaTools.cmake20 foreach(root ${SCA_ROOT})
21 if(EXISTS ${root}/cmake/sca/${ZEPHYR_SCA_VARIANT}/sca.cmake)
22 include(${root}/cmake/sca/${ZEPHYR_SCA_VARIANT}/sca.cmake)
Droot.cmake18 # If a root is defined it will check the list of paths in the root and convert
19 # any relative path to absolute path and update the root list.
20 # If a root is undefined it will still be undefined when this module has loaded.
45 # Zephyr used in unittest mode, use dedicated unittest root.
/Zephyr-4.3.0/scripts/west_commands/tests/west_build/
Dtest_resolve_build_dir.py11 root = Path(cwd.anchor) variable
12 TEST_CWD = root / 'path' / 'to' / 'my' / 'current' / 'cwd'

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