| /Zephyr-4.3.0/boards/snps/nsim/arc_classic/ |
| D | nsim_nsim_hs5x_smp_12cores.dts | 20 cpu@0 {
21 device_type = "cpu";
26 cpu@1 {
27 device_type = "cpu";
32 cpu@2 {
33 device_type = "cpu";
38 cpu@3 {
39 device_type = "cpu";
44 cpu@4 {
45 device_type = "cpu";
[all …]
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| D | nsim_nsim_hs6x_smp_12cores.dts | 20 cpu@0 {
21 device_type = "cpu";
26 cpu@1 {
27 device_type = "cpu";
32 cpu@2 {
33 device_type = "cpu";
38 cpu@3 {
39 device_type = "cpu";
44 cpu@4 {
45 device_type = "cpu";
[all …]
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| /Zephyr-4.3.0/kernel/ |
| D | usage.c | 36 static void sched_cpu_update_usage(struct _cpu *cpu, uint32_t cycles) in sched_cpu_update_usage() argument
38 if (!cpu->usage->track_usage) { in sched_cpu_update_usage()
42 if (cpu->current != cpu->idle_thread) { in sched_cpu_update_usage()
43 cpu->usage->total += cycles; in sched_cpu_update_usage()
46 cpu->usage->current += cycles; in sched_cpu_update_usage()
48 if (cpu->usage->longest < cpu->usage->current) { in sched_cpu_update_usage()
49 cpu->usage->longest = cpu->usage->current; in sched_cpu_update_usage()
52 cpu->usage->current = 0; in sched_cpu_update_usage()
53 cpu->usage->num_windows++; in sched_cpu_update_usage()
58 #define sched_cpu_update_usage(cpu, cycles) do { } while (0) argument
[all …]
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| /Zephyr-4.3.0/tests/boards/intel_adsp/smoke/src/ |
| D | cpus.c | 45 static void run_on_cpu(int cpu, void (*fn)(void *), void *arg, bool wait) in run_on_cpu() argument
47 __ASSERT_NO_MSG(cpu < arch_num_cpus()); in run_on_cpu()
53 k_thread_create(&run_on_threads[cpu], run_on_stacks[cpu], RUN_ON_STACKSZ, in run_on_cpu()
54 run_on_cpu_threadfn, fn, arg, (void *)&run_on_flags[cpu], in run_on_cpu()
56 k_thread_cpu_mask_clear(&run_on_threads[cpu]); in run_on_cpu()
57 k_thread_cpu_mask_enable(&run_on_threads[cpu], cpu); in run_on_cpu()
58 run_on_flags[cpu] = false; in run_on_cpu()
59 k_thread_start(&run_on_threads[cpu]); in run_on_cpu()
62 while (!run_on_flags[cpu]) { in run_on_cpu()
66 k_thread_abort(&run_on_threads[cpu]); in run_on_cpu()
[all …]
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| /Zephyr-4.3.0/dts/arm64/rockchip/ |
| D | rk3588s.dtsi | 18 cpu@0 {
19 device_type = "cpu";
24 cpu@1 {
25 device_type = "cpu";
30 cpu@2 {
31 device_type = "cpu";
36 cpu@3 {
37 device_type = "cpu";
42 cpu@4 {
43 device_type = "cpu";
[all …]
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| D | rk3399.dtsi | 19 cpu@0 {
20 device_type = "cpu";
25 cpu@1 {
26 device_type = "cpu";
31 cpu@2 {
32 device_type = "cpu";
37 cpu@3 {
38 device_type = "cpu";
43 cpu@4 {
44 device_type = "cpu";
[all …]
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| /Zephyr-4.3.0/dts/riscv/qemu/ |
| D | virt-riscv32.dtsi | 13 cpu@0 {
17 cpu@1 {
21 cpu@2 {
25 cpu@3 {
29 cpu@4 {
33 cpu@5 {
37 cpu@6 {
41 cpu@7 {
|
| D | virt-riscv64.dtsi | 13 cpu@0 {
17 cpu@1 {
21 cpu@2 {
25 cpu@3 {
29 cpu@4 {
33 cpu@5 {
37 cpu@6 {
41 cpu@7 {
|
| D | virt-riscv.dtsi | 40 cpu@0 {
41 device_type = "cpu";
47 compatible = "riscv,cpu-intc";
54 cpu@1 {
55 device_type = "cpu";
61 compatible = "riscv,cpu-intc";
68 cpu@2 {
69 device_type = "cpu";
75 compatible = "riscv,cpu-intc";
82 cpu@3 {
[all …]
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| /Zephyr-4.3.0/drivers/interrupt_controller/ |
| D | intc_esp32.c | 73 if (vd->cpu > to_insert->cpu) { in insert_vector_desc()
76 if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) { in insert_vector_desc()
93 static struct vector_desc_t *find_desc_for_int(int intno, int cpu) in find_desc_for_int() argument
98 if (vd->cpu == cpu && vd->intno == intno) { in find_desc_for_int()
111 static struct vector_desc_t *get_desc_for_int(int intno, int cpu) in get_desc_for_int() argument
113 struct vector_desc_t *vd = find_desc_for_int(intno, cpu); in get_desc_for_int()
123 newvd->cpu = cpu; in get_desc_for_int()
135 static struct vector_desc_t *find_desc_for_source(int source, int cpu) in find_desc_for_source() argument
141 if (vd->source == source && cpu == vd->cpu) { in find_desc_for_source()
144 } else if (vd->cpu == cpu) { in find_desc_for_source()
[all …]
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| /Zephyr-4.3.0/boards/khadas/edge2/ |
| D | khadas_edge2.dts | 21 /delete-node/ cpu@1;
22 /delete-node/ cpu@2;
23 /delete-node/ cpu@3;
24 /delete-node/ cpu@4;
25 /delete-node/ cpu@5;
26 /delete-node/ cpu@6;
27 /delete-node/ cpu@7;
|
| /Zephyr-4.3.0/soc/intel/intel_adsp/ace/ |
| D | power.c | 280 uint32_t cpu = arch_proc_id(); in pm_state_set() local
287 core_desc[cpu].intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
292 core_desc[cpu].bctl = DSPCS.bootctl[cpu].bctl; in pm_state_set()
293 DSPCS.bootctl[cpu].bctl &= ~DSPBR_BCTL_WAITIPCG; in pm_state_set()
294 if (cpu == 0) { in pm_state_set()
295 soc_cpus_active[cpu] = false; in pm_state_set()
320 _save_core_context(cpu); in pm_state_set()
350 power_gate_entry(cpu); in pm_state_set()
356 battr = DSPCS.bootctl[cpu].battr & (~LPSCTL_BATTR_MASK); in pm_state_set()
358 DSPCS.bootctl[cpu].bctl &= ~DSPBR_BCTL_WAITIPPG; in pm_state_set()
[all …]
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| /Zephyr-4.3.0/dts/arm64/ti/ |
| D | ti_am6234_a53.dtsi | 14 cpu@1 {
15 device_type = "cpu";
20 cpu@2 {
21 device_type = "cpu";
26 cpu@3 {
27 device_type = "cpu";
|
| D | ti_am6254_a53.dtsi | 14 cpu@1 {
15 device_type = "cpu";
20 cpu@2 {
21 device_type = "cpu";
26 cpu@3 {
27 device_type = "cpu";
|
| /Zephyr-4.3.0/boards/qemu/arc/ |
| D | board.cmake | 7 set(QEMU_FLAGS_${ARCH} -cpu arcem)
10 set(QEMU_FLAGS_${ARCH} -cpu archs)
14 set(QEMU_FLAGS_${ARCH} -cpu hs5x)
18 set(QEMU_FLAGS_${ARCH} -cpu hs6x)
33 -global cpu.firq=false
34 -global cpu.num-irqlevels=15
35 -global cpu.num-irq=25
36 -global cpu.ext-irq=20
37 -global cpu.freq_hz=10000000
38 -global cpu.timer0=true
[all …]
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| /Zephyr-4.3.0/dts/xtensa/intel/ |
| D | intel_adsp_ace30_ptl.dtsi | 11 cpu3: cpu@3 {
12 device_type = "cpu";
15 cpu-power-states = <&d0i3 &d3>;
18 cpu4: cpu@4 {
19 device_type = "cpu";
22 cpu-power-states = <&d0i3 &d3>;
|
| D | intel_adsp_ace40_nvl.dtsi | 11 cpu2: cpu@2 {
12 device_type = "cpu";
15 cpu-power-states = <&d0i3 &d3>;
18 cpu3: cpu@3 {
19 device_type = "cpu";
22 cpu-power-states = <&d0i3 &d3>;
|
| /Zephyr-4.3.0/soc/intel/intel_adsp/common/ |
| D | multiprocessing.c | 29 uint32_t cpu; member
35 const uint32_t *z_mp_start_cpu = &start_rec.cpu;
103 _cpu_t *cpu = &_kernel.cpus[start_rec.cpu]; in z_mp_entry() local
105 __asm__ volatile("wsr %0, " ZSR_CPU_STR :: "r"(cpu)); in z_mp_entry()
107 soc_mp_startup(start_rec.cpu); in z_mp_entry()
108 soc_cpus_active[start_rec.cpu] = true; in z_mp_entry()
128 start_rec.cpu = cpu_num; in arch_cpu_start()
|
| /Zephyr-4.3.0/tests/benchmarks/ipi_metric/boards/ |
| D | qemu_x86_64.overlay | 3 cpu@2 {
4 device_type = "cpu";
9 cpu@3 {
10 device_type = "cpu";
|
| /Zephyr-4.3.0/boards/qemu/riscv32_xip/doc/ |
| D | index.rst | 35 thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
36 thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
37 thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
38 thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
39 thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
40 thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
41 thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
42 thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
43 thread_a: Hello World from cpu 0 on qemu_riscv32_xip!
44 thread_b: Hello World from cpu 0 on qemu_riscv32_xip!
[all …]
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| /Zephyr-4.3.0/include/zephyr/arch/x86/ |
| D | arch_inlines.h | 22 struct _cpu *cpu; in arch_curr_cpu() local
25 : "=r" (cpu) in arch_curr_cpu()
26 : "i" (offsetof(x86_tss64_t, cpu))); in arch_curr_cpu()
28 return cpu; in arch_curr_cpu()
|
| /Zephyr-4.3.0/boards/beagle/beaglev_fire/ |
| D | beaglev_fire_polarfire_e51.dts | 8 cpu@1 {
12 cpu@2 {
16 cpu@3 {
20 cpu@4 {
|
| /Zephyr-4.3.0/dts/arm/nxp/ |
| D | nxp_s32k566_m7.dtsi | 16 cpu@0 {
17 device_type = "cpu";
23 cpu@1 {
24 device_type = "cpu";
30 cpu@2 {
31 device_type = "cpu";
37 cpu@3 {
38 device_type = "cpu";
|
| /Zephyr-4.3.0/boards/qemu/riscv32e/doc/ |
| D | index.rst | 36 thread_a: Hello World from cpu 0 on qemu_riscv32e!
37 thread_b: Hello World from cpu 0 on qemu_riscv32e!
38 thread_a: Hello World from cpu 0 on qemu_riscv32e!
39 thread_b: Hello World from cpu 0 on qemu_riscv32e!
40 thread_a: Hello World from cpu 0 on qemu_riscv32e!
41 thread_b: Hello World from cpu 0 on qemu_riscv32e!
42 thread_a: Hello World from cpu 0 on qemu_riscv32e!
43 thread_b: Hello World from cpu 0 on qemu_riscv32e!
44 thread_a: Hello World from cpu 0 on qemu_riscv32e!
45 thread_b: Hello World from cpu 0 on qemu_riscv32e!
[all …]
|
| /Zephyr-4.3.0/tests/kernel/smp_metairq/boards/ |
| D | qemu_cortex_a53_qemu_cortex_a53_smp.overlay | 9 cpu@2 {
10 device_type = "cpu";
15 cpu@3 {
16 device_type = "cpu";
|
