Searched refs:aligned_addr (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-4.3.0/drivers/cache/ |
| D | cache_aspeed.c | 163 uint32_t aligned_addr, i, n; in cache_data_invd_range() local
177 n = get_n_cacheline((uint32_t)addr, size, &aligned_addr); in cache_data_invd_range()
181 syscon_write_reg(dev, CACHE_INVALID_REG, DCACHE_INVALID(aligned_addr)); in cache_data_invd_range()
182 aligned_addr += CACHE_LINE_SIZE; in cache_data_invd_range()
224 uint32_t aligned_addr, i, n; in cache_instr_invd_range() local
233 n = get_n_cacheline((uint32_t)addr, size, &aligned_addr); in cache_instr_invd_range()
242 syscon_write_reg(dev, CACHE_INVALID_REG, ICACHE_INVALID(aligned_addr)); in cache_instr_invd_range()
243 aligned_addr += CACHE_LINE_SIZE; in cache_instr_invd_range()
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| /Zephyr-4.3.0/soc/intel/intel_adsp/common/include/ |
| D | intel_adsp_hda.h | 170 uint32_t aligned_addr = addr & HDA_ALIGN_MASK; in intel_adsp_hda_set_buffer() local
173 __ASSERT(aligned_addr == addr, "Buffer must be 128 byte aligned"); in intel_adsp_hda_set_buffer()
185 __ASSERT(aligned_addr >= _INTEL_ADSP_BASE in intel_adsp_hda_set_buffer()
186 && aligned_addr < _INTEL_ADSP_BASE + _INTEL_ADSP_SIZE, in intel_adsp_hda_set_buffer()
188 __ASSERT(aligned_addr + aligned_size < _INTEL_ADSP_BASE + _INTEL_ADSP_SIZE, in intel_adsp_hda_set_buffer()
199 *DGBBA(base, regblock_size, sid) = aligned_addr; in intel_adsp_hda_set_buffer()
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| /Zephyr-4.3.0/drivers/flash/ |
| D | flash_mchp_nvmctrl_g1.c | 581 uint32_t aligned_addr = *offset & ~(FLASH_MCHP_DOUBLE_WORD_SIZE - 1); in flash_handle_unaligned_start() local
583 size_t start_offset = (*offset - aligned_addr); in flash_handle_unaligned_start()
584 const uint8_t *src = (const uint8_t *)aligned_addr; in flash_handle_unaligned_start()
599 ret = flash_doubleword_write(dev, doubleword_buf, aligned_addr); in flash_handle_unaligned_start()
601 LOG_ERR("double word write failed at 0x%lx", (long)aligned_addr); in flash_handle_unaligned_start()
630 uint32_t aligned_addr = offset; in flash_handle_unaligned_end() local
632 const uint8_t *src = (const uint8_t *)aligned_addr; in flash_handle_unaligned_end()
644 ret = flash_doubleword_write(dev, doubleword_buf, aligned_addr); in flash_handle_unaligned_end()
646 LOG_ERR("double word write failed at 0x%lx", (long)aligned_addr); in flash_handle_unaligned_end()
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| /Zephyr-4.3.0/arch/xtensa/core/ |
| D | mpu.c | 1012 uintptr_t aligned_addr; in arch_buffer_validate() local
1017 aligned_addr = ROUND_DOWN((uintptr_t)addr, XCHAL_MPU_ALIGN); in arch_buffer_validate()
1018 addr_offset = (uintptr_t)addr - aligned_addr; in arch_buffer_validate()
1023 uint32_t probed = xtensa_pptlb_probe(aligned_addr + offset); in arch_buffer_validate()
1083 uintptr_t aligned_addr; in xtensa_mem_kernel_has_access() local
1088 aligned_addr = ROUND_DOWN((uintptr_t)addr, XCHAL_MPU_ALIGN); in xtensa_mem_kernel_has_access()
1089 addr_offset = (uintptr_t)addr - aligned_addr; in xtensa_mem_kernel_has_access()
1094 uint32_t probed = xtensa_pptlb_probe(aligned_addr + offset); in xtensa_mem_kernel_has_access()
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| /Zephyr-4.3.0/include/zephyr/kernel/ |
| D | mm.h | 293 size_t k_mem_region_align(uintptr_t *aligned_addr, size_t *aligned_size,
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| /Zephyr-4.3.0/tests/kernel/mem_protect/mem_map/src/ |
| D | main.c | 60 uintptr_t aligned_addr; in ZTEST() local
89 k_mem_region_align(&aligned_addr, &aligned_size, (uintptr_t)mapped_rw, in ZTEST()
94 sys_cache_data_flush_and_invd_range((void *)aligned_addr, aligned_size); in ZTEST()
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| /Zephyr-4.3.0/kernel/ |
| D | mmu.c | 1008 size_t k_mem_region_align(uintptr_t *aligned_addr, size_t *aligned_size, in k_mem_region_align() argument
1016 *aligned_addr = ROUND_DOWN(addr, align); in k_mem_region_align()
1017 addr_offset = addr - *aligned_addr; in k_mem_region_align()
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