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Searched refs:sys_set_bits (Results 1 – 25 of 36) sorted by relevance

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/Zephyr-4.2.1/drivers/gpio/
Dgpio_rp1.c84 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_PERI); in gpio_rp1_pin_configure()
87 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_PERI); in gpio_rp1_pin_configure()
90 sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_RIO); in gpio_rp1_pin_configure()
107 sys_set_bits(PADS_CTRL(data->pads_base, pin), in gpio_rp1_pin_configure()
116 sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_UP_ENABLE); in gpio_rp1_pin_configure()
118 sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_DOWN_ENABLE); in gpio_rp1_pin_configure()
139 sys_set_bits(RIO_OUT_CLR(data->rio_base), mask); in gpio_rp1_port_set_masked_raw()
142 sys_set_bits(RIO_OUT_SET(data->rio_base), (value & mask)); in gpio_rp1_port_set_masked_raw()
152 sys_set_bits(RIO_OUT_SET(data->rio_base), pins); in gpio_rp1_port_set_bits_raw()
162 sys_set_bits(RIO_OUT_CLR(data->rio_base), pins); in gpio_rp1_port_clear_bits_raw()
[all …]
Dgpio_brcmstb.c73 sys_set_bits(data->base + GIO_DATA, (value & mask)); in gpio_brcmstb_port_set_masked_raw()
82 sys_set_bits(data->base + GIO_DATA, pins); in gpio_brcmstb_port_set_bits_raw()
Dgpio_altera_pio.c96 sys_set_bits(addr, BIT(pin)); in gpio_altera_configure()
148 sys_set_bits(addr, mask); in gpio_altera_port_set_bits_raw()
236 sys_set_bits(addr, BIT(pin)); in gpio_altera_pin_interrupt_configure()
/Zephyr-4.2.1/drivers/pwm/
Dpwm_sf32lb_gpt.c73 sys_set_bits(config->base + GPT_CCER, GPT_CCER_CC1P << pos); in pwm_sf32lb_set_cycles()
82 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC1PE); in pwm_sf32lb_set_cycles()
83 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1); in pwm_sf32lb_set_cycles()
87 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC2PE); in pwm_sf32lb_set_cycles()
88 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1); in pwm_sf32lb_set_cycles()
92 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC3PE); in pwm_sf32lb_set_cycles()
93 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1); in pwm_sf32lb_set_cycles()
97 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC4PE); in pwm_sf32lb_set_cycles()
98 sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1); in pwm_sf32lb_set_cycles()
/Zephyr-4.2.1/drivers/sdhc/
Dsdhc_cdns_ll.c382 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_HRS09, CDNS_HRS09_RDCMD_EN_BIT | in sdhc_cdns_host_set_clk()
519 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_HRS09, CDNS_HRS09_RDCMD_EN_BIT | in sdhc_cdns_set_clk()
607 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_SW); in sdhc_cdns_send_cmd()
608 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
609 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS15, SRS15_VAL_GEN); in sdhc_cdns_send_cmd()
615 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_READ); in sdhc_cdns_send_cmd()
616 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
617 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS15, SRS15_VAL_RD_WR); in sdhc_cdns_send_cmd()
624 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS10, SRS10_VAL_READ); in sdhc_cdns_send_cmd()
625 sys_set_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, SRS11_VAL_GEN); in sdhc_cdns_send_cmd()
[all …]
/Zephyr-4.2.1/drivers/clock_control/
Dclock_stm32_mco.c47 sys_set_bits( in stm32_mco_init()
53 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_mco_init()
63 sys_set_bits( in stm32_mco_init()
Dclock_stm32_ll_mp2.c25 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); in stm32_clock_control_on()
Dclock_agilex_ll.c21 #define mmio_setbits_32(addr, mask) sys_set_bits((addr), (mask))
Dclock_stm32_ll_u3.c132 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); in stm32_clock_control_on()
180 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_wb0.c221 sys_set_bits(reg, pclken->enr); in stm32_clock_control_on()
267 sys_set_bits(reg, STM32_DT_CLKSEL_VAL_GET(pclken->enr) << shift); in stm32_clock_control_configure()
Dclock_stm32_ll_wba.c80 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
132 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_n6.c221 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
225 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + STM32_CLOCK_LP_BUS_SHIFT, in stm32_clock_control_on()
277 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr), in stm32_clock_control_configure()
/Zephyr-4.2.1/drivers/ethernet/
Deth_cyclonev.c83 sys_set_bits(RSTMGR_PERMODRST_ADDR, Rstmgr_Permodrst_Emac_Set_Msk[instance]); in eth_cyclonev_reset()
180 sys_set_bits(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr), EMAC_DMA_MODE_SWR_SET_MSK); in eth_cyclonev_software_reset()
335 sys_set_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
484 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR( in eth_cyclonev_send()
488 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR( in eth_cyclonev_send()
963 sys_set_bits(EMAC_DMA_INT_EN_ADDR(p->base_addr), interrupt_mask); in eth_cyclonev_probe()
1026 sys_set_bits(EMAC_GMAC_INT_MSK_ADDR(p->base_addr), in eth_cyclonev_probe()
1065 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1067 sys_set_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_start()
1071 sys_set_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_start()
[all …]
/Zephyr-4.2.1/drivers/input/
Dinput_tsc_keys.c88 sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC); in stm32_tsc_start()
91 sys_set_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE); in stm32_tsc_start()
204 sys_set_bits((mem_addr_t)&config->tsc->CR, (((config->ctph - 1) << 4) | (config->ctpl - 1)) in stm32_tsc_init()
208 sys_set_bits((mem_addr_t)&config->tsc->CR, config->ssd << TSC_CR_SSD_Pos); in stm32_tsc_init()
211 sys_set_bits((mem_addr_t)&config->tsc->CR, config->pgpsc << TSC_CR_PGPSC_Pos); in stm32_tsc_init()
214 sys_set_bits((mem_addr_t)&config->tsc->CR, config->max_count << TSC_CR_MCV_Pos); in stm32_tsc_init()
268 sys_set_bits((mem_addr_t)&config->tsc->IOCCR, in stm32_tsc_init()
272 sys_set_bits((mem_addr_t)&config->tsc->IOSCR, in stm32_tsc_init()
285 sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC); in stm32_tsc_init()
/Zephyr-4.2.1/soc/st/stm32/common/
Dstm32_bitops.h24 sys_set_bits((mem_addr_t)addr, mask); in stm32_reg_set_bits()
/Zephyr-4.2.1/drivers/spi/
Dspi_andes_atcspi200.c67 sys_set_bits(SPI_TIMIN(cfg->base), sclk_div); in spi_config()
78 sys_set_bits(SPI_TFMAT(cfg->base), (data_len << TFMAT_DATA_LEN_OFFSET)); in spi_config()
82 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
88 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
95 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
104 sys_set_bits(SPI_CTRL(cfg->base), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET); in spi_config()
105 sys_set_bits(SPI_CTRL(cfg->base), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET); in spi_config()
204 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_enable()
218 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_enable()
600 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_FIFO_RST_MSK); in transceive()
[all …]
Dspi_egis_et171.c119 sys_set_bits(SPI_TIMIN(cfg->base), sclk_div); in spi_config()
130 sys_set_bits(SPI_TFMAT(cfg->base), (data_len << TFMAT_DATA_LEN_OFFSET)); in spi_config()
134 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
140 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
147 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
156 sys_set_bits(SPI_CTRL(cfg->base), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET); in spi_config()
157 sys_set_bits(SPI_CTRL(cfg->base), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET); in spi_config()
258 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_enable()
272 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_enable()
669 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_FIFO_RST_MSK); in transceive()
[all …]
Dspi_sf32lb.c57 sys_set_bits(cfg->base + SPI_STATUS, SPI_STATUS_ROR | SPI_STATUS_TUR); in spi_sf32lb_complete()
213 sys_set_bits(cfg->base + SPI_FIFO_CTRL, SPI_FIFO_CTRL_TSRE | SPI_FIFO_CTRL_RSRE); in spi_sf32lb_reset_fifos()
389 sys_set_bits(cfg->base + SPI_STATUS, SPI_STATUS_ROR | SPI_STATUS_TUR | SPI_STATUS_TINT); in spi_sf32lb_transceive()
431 sys_set_bits(cfg->base + SPI_STATUS, SPI_STATUS_ROR | SPI_STATUS_TUR); in spi_sf32lb_transceive_async()
/Zephyr-4.2.1/include/zephyr/arch/common/
Dsys_bitops.h45 static ALWAYS_INLINE void sys_set_bits(mem_addr_t addr, unsigned int mask) in sys_set_bits() function
/Zephyr-4.2.1/drivers/crc/
Dcrc_sf32lb.c198 sys_set_bits(config->base + CRC_CR_OFFSET, CRC_CR_DATASIZE_Msk); in crc_sf32lb_update()
217 sys_set_bits(config->base + CRC_CR_OFFSET, in crc_sf32lb_update()
/Zephyr-4.2.1/drivers/adc/
Dadc_sf32lb.c278 sys_set_bits(config->base + ADC_CTRL_REG, GPADC_ADC_CTRL_REG_FRC_EN_ADC | in adc_sf32lb_init()
281 sys_set_bits(config->base + ADC_CFG_REG1, GPADC_ADC_CFG_REG1_ANAU_GPADC_SE | in adc_sf32lb_init()
/Zephyr-4.2.1/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h66 sys_set_bits(ggpio_reg, USB_DWC2_GGPIO_STM32_PWRDWN | USB_DWC2_GGPIO_STM32_VBDEN); in stm32f4_fsotg_enable_phy()
285 sys_set_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); in usbhs_post_hibernation_entry()
493 sys_set_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); in usbhs_post_hibernation_entry()
Dudc_dwc2.c385 sys_set_bits(reg, epmsk); in dwc2_set_epint()
1240 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PMUACTV); in dwc2_enter_hibernation()
1244 sys_set_bits(pcgcctl_reg, USB_DWC2_PCGCCTL_STOPPCLK); in dwc2_enter_hibernation()
1248 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PMUINTSEL); in dwc2_enter_hibernation()
1252 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_LINESTAGECHANGEMSK | in dwc2_enter_hibernation()
1259 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNCLMP); in dwc2_enter_hibernation()
1263 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNSWTCH); in dwc2_enter_hibernation()
1292 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_RESTORE); in dwc2_exit_hibernation()
1307 sys_set_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNRST_N); in dwc2_exit_hibernation()
1333 sys_set_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_PWRONPRGDONE); in dwc2_exit_hibernation()
[all …]
/Zephyr-4.2.1/drivers/i2c/
Di2c_sf32lb.c307 sys_set_bits(cfg->base + I2C_IER, I2C_IER_RFIE | I2C_IER_MSDIE | I2C_IER_BEDIE); in i2c_sf32lb_master_recv()
409 sys_set_bits(cfg->base + I2C_CR, I2C_CR_IUE | I2C_CR_MSDE); in i2c_sf32lb_transfer()
488 sys_set_bits(config->base + I2C_CR, I2C_CR_IUE | I2C_CR_SCLE); in i2c_sf32lb_init()
/Zephyr-4.2.1/drivers/flash/
Dflash_andes_qspi.c725 sys_set_bits(QSPI_TIMIN(base), TIMIN_SCLK_DIV_MSK); in qspi_andes_configure()
735 sys_set_bits(QSPI_TFMAT(base), (7 << TFMAT_DATA_LEN_OFFSET)); in qspi_andes_configure()
741 sys_set_bits(QSPI_CTRL(base), TX_FIFO_THRESHOLD); in qspi_andes_configure()
742 sys_set_bits(QSPI_CTRL(base), RX_FIFO_THRESHOLD); in qspi_andes_configure()

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