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Searched refs:clock_dev (Results 1 – 25 of 190) sorted by relevance

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/Zephyr-4.2.1/tests/drivers/clock_control/nrf_onoff_and_bt/src/
Dmain.c26 static const struct device *const clock_dev = DEVICE_DT_GET_ONE(nordic_nrf_clock); variable
34 zassert_true(device_is_ready(clock_dev)); in setup()
130 check_hf_status(clock_dev, true, true); in ZTEST()
145 check_hf_status(clock_dev, false, true); in ZTEST()
216 check_hf_status(clock_dev, true, false); in ZTEST()
230 check_hf_status(clock_dev, false, true); in ZTEST()
242 check_hf_status(clock_dev, true, false); in ZTEST()
250 check_hf_status(clock_dev, true, false); in ZTEST()
254 check_hf_status(clock_dev, false, false); in ZTEST()
264 check_hf_status(clock_dev, true, false); in ZTEST()
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/Zephyr-4.2.1/drivers/dac/
Ddac_esp32.c23 const struct device *clock_dev; member
61 if (!cfg->clock_dev) { in dac_esp32_init()
66 if (!device_is_ready(cfg->clock_dev)) { in dac_esp32_init()
71 if (clock_control_on(cfg->clock_dev, (clock_control_subsys_t)cfg->clock_subsys) != 0) { in dac_esp32_init()
88 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
Ddac_silabs_vdac.c27 const struct device *clock_dev; member
48 err = clock_control_on(config->clock_dev, in vdac_init()
56 err = clock_control_get_rate(config->clock_dev, in vdac_init()
147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-4.2.1/drivers/clock_control/
Dclock_control_si32_ahb.c24 const struct device *clock_dev; member
58 if (!device_is_ready(config->clock_dev)) { in clock_control_si32_ahb_init()
65 ret = clock_control_set_rate(config->clock_dev, NULL, &freq); in clock_control_si32_ahb_init()
71 ret = clock_control_on(config->clock_dev, NULL); in clock_control_si32_ahb_init()
98 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dclock_control_si32_apb.c19 const struct device *clock_dev; member
38 const int ret = clock_control_get_rate(config->clock_dev, NULL, rate); in clock_control_si32_apb_get_rate()
59 if (!device_is_ready(config->clock_dev)) { in clock_control_si32_apb_init()
75 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dclock_control_renesas_rx_pll_cgc.c48 ret = clock_control_get_rate(config->clock_dev, NULL, &clock_dev_freq); in clock_control_renesas_rx_pll_get_rate()
73 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))), \
/Zephyr-4.2.1/drivers/opamp/
Dopamp_mcux_opamp_fast.c23 const struct device *clock_dev; member
63 if (!device_is_ready(config->clock_dev)) { in mcux_opamp_fast_init()
68 ret = clock_control_on(config->clock_dev, config->clock_subsys); in mcux_opamp_fast_init()
92 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-4.2.1/drivers/memc/
Dmemc_silabs_siwx91x_qspi.c20 const struct device *clock_dev; member
42 if (config->clock_dev) { in siwx91x_memc_init()
43 ret = device_is_ready(config->clock_dev); in siwx91x_memc_init()
47 ret = clock_control_on(config->clock_dev, config->clock_subsys); in siwx91x_memc_init()
65 .clock_dev = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR(0)),
/Zephyr-4.2.1/drivers/pwm/
Dpwm_silabs_letimer.c23 const struct device *clock_dev; member
85 err = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg, in silabs_letimer_pwm_get_cycles_per_sec()
102 err = clock_control_on(config->clock_dev, in silabs_letimer_pwm_pm_action()
117 err = clock_control_off(config->clock_dev, in silabs_letimer_pwm_pm_action()
140 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg); in silabs_letimer_pwm_init()
164 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(inst))), \
Dpwm_rv32m1_tpm.c28 const struct device *clock_dev; member
144 if (!device_is_ready(config->clock_dev)) { in rv32m1_tpm_init()
149 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in rv32m1_tpm_init()
154 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in rv32m1_tpm_init()
191 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_wch_gptm.c45 const struct device *clock_dev; member
124 err = clock_control_get_rate(config->clock_dev, clock_sys, &clock_rate); in pwm_wch_gptm_get_cycles_per_sec()
145 clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id); in pwm_wch_gptm_init()
166 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(idx))), \
/Zephyr-4.2.1/drivers/pinctrl/
Dpinctrl_nxp_port.c38 const struct device *clock_dev; member
60 if (!device_is_ready(config->clock_dev)) { in pinctrl_mcux_init()
65 err = clock_control_on(config->clock_dev, config->clock_subsys); in pinctrl_mcux_init()
89 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-4.2.1/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c22 ret = clock_control_on(config->clock_dev, config->clock_subsys); in nxp_enet_qos_init()
35 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-4.2.1/drivers/entropy/
Dentropy_esp32.c99 const struct device *clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(trng0))); in entropy_esp32_init() local
103 if (!device_is_ready(clock_dev)) { in entropy_esp32_init()
107 clock_control_on(clock_dev, clock_subsys); in entropy_esp32_init()
/Zephyr-4.2.1/drivers/misc/ethos_u/
Dethos_u_renesas.c23 const struct device *clock_dev; member
47 if (!device_is_ready(config->clock_dev)) { in ethos_u_renesas_ra_init()
52 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_subsys); in ethos_u_renesas_ra_init()
110 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
/Zephyr-4.2.1/drivers/misc/interconn/renesas_elc/
Drenesas_ra_elc.c19 const struct device *clock_dev; member
107 if (!device_is_ready(cfg->clock_dev)) { in renesas_ra_elc_init()
111 ret = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys); in renesas_ra_elc_init()
139 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-4.2.1/drivers/retained_mem/
Dretained_mem_silabs_buram.c32 const struct device *clock_dev; member
69 if (!config->clock_dev) { in silabs_buram_init()
74 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg); in silabs_buram_init()
141 .clock_dev = COND_CODE_1(DT_INST_CLOCKS_HAS_IDX(inst, 0), \
/Zephyr-4.2.1/drivers/i2c/
Di2c_rv32m1_lpi2c.c27 const struct device *clock_dev; member
86 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_configure()
218 if (!device_is_ready(config->clock_dev)) { in rv32m1_lpi2c_init()
223 err = clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_lpi2c_init()
229 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_init()
272 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-4.2.1/drivers/watchdog/
Dwdt_mcux_wdog32.c33 const struct device *clock_dev; member
85 if (!device_is_ready(config->clock_dev)) { in mcux_wdog32_setup()
90 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) { in mcux_wdog32_setup()
132 if (!device_is_ready(config->clock_dev)) { in mcux_wdog32_install_timeout()
137 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq)) { in mcux_wdog32_install_timeout()
233 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dwdt_mcux_wdog.c23 const struct device *clock_dev; member
82 if (!device_is_ready(config->clock_dev)) { in mcux_wdog_install_timeout()
87 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog_install_timeout()
170 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
/Zephyr-4.2.1/drivers/timer/
Drenesas_rza2m_os_timer.c188 const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); in sys_clock_driver_init() local
191 if (!device_is_ready(clock_dev)) { in sys_clock_driver_init()
195 ret = clock_control_on(clock_dev, (clock_control_subsys_t)&clock_subsys); in sys_clock_driver_init()
201 ret = clock_control_get_rate(clock_dev, (clock_control_subsys_t)&clock_subsys, in sys_clock_driver_init()
/Zephyr-4.2.1/drivers/video/
Dvideo_mcux_mipi_csi2rx.c33 const struct device *clock_dev; member
76 ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_root, &root_clk_rate); in mipi_csi2rx_update_settings()
82 ret = clock_control_set_rate(drv_data->clock_dev, drv_data->clock_root, in mipi_csi2rx_update_settings()
89 ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_ui, &ui_clk_rate); in mipi_csi2rx_update_settings()
96 drv_data->clock_dev, drv_data->clock_ui, in mipi_csi2rx_update_settings()
303 ret = clock_control_set_rate(drv_data->clock_dev, drv_data->clock_esc, in mipi_csi2rx_init()
317 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-4.2.1/drivers/interrupt_controller/
Dintc_rv32m1_intmux.c44 const struct device *clock_dev; member
147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
158 if (!device_is_ready(config->clock_dev)) { in rv32m1_intmux_init()
163 clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_intmux_init()
/Zephyr-4.2.1/drivers/comparator/
Dcomparator_silabs_acmp.c25 const struct device *clock_dev; member
45 err = clock_control_on(config->clock_dev, in acmp_pm_action()
61 err = clock_control_off(config->clock_dev, in acmp_pm_action()
84 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg); in acmp_init()
233 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-4.2.1/drivers/can/
Dcan_mcux_mcan.c27 const struct device *clock_dev; member
80 return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys, in mcux_mcan_get_core_clock()
91 if (!device_is_ready(mcux_config->clock_dev)) { in mcux_mcan_init()
111 err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys); in mcux_mcan_init()
207 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \

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