| /Zephyr-4.2.1/subsys/net/lib/dns/ |
| D | dns_cache.c | 13 static void dns_cache_clean(struct dns_cache const *cache);
15 int dns_cache_flush(struct dns_cache *cache) in dns_cache_flush() argument
17 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_flush()
18 for (size_t i = 0; i < cache->size; i++) { in dns_cache_flush()
19 cache->entries[i].in_use = false; in dns_cache_flush()
21 k_mutex_unlock(cache->lock); in dns_cache_flush()
26 int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo, in dns_cache_add() argument
33 if (cache == NULL || query == NULL || addrinfo == NULL || ttl == 0) { in dns_cache_add()
44 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_add()
48 dns_cache_clean(cache); in dns_cache_add()
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| D | dns_cache.h | 56 int dns_cache_flush(struct dns_cache *cache);
71 int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo,
82 int dns_cache_remove(struct dns_cache *cache, char const *query);
98 int dns_cache_find(struct dns_cache const *cache, const char *query, enum dns_query_type type,
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| /Zephyr-4.2.1/subsys/logging/ |
| D | log_cache.c | 24 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config) in log_cache_init() argument
26 sys_slist_init(&cache->active); in log_cache_init()
27 sys_slist_init(&cache->idle); in log_cache_init()
41 sys_slist_append(&cache->idle, &entry->node); in log_cache_init()
45 cache->cmp = config->cmp; in log_cache_init()
46 cache->item_size = config->item_size; in log_cache_init()
47 cache->hit = 0; in log_cache_init()
48 cache->miss = 0; in log_cache_init()
53 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data) in log_cache_get() argument
60 SYS_SLIST_FOR_EACH_CONTAINER(&cache->active, entry, node) { in log_cache_get()
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| D | log_cache.h | 39 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config);
50 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data);
58 void log_cache_put(struct log_cache *cache, uint8_t *data);
68 void log_cache_release(struct log_cache *cache, uint8_t *data);
76 static inline uint32_t log_cache_get_hit(struct log_cache *cache) in log_cache_get_hit() argument
78 return cache->hit; in log_cache_get_hit()
87 static inline uint32_t log_cache_get_miss(struct log_cache *cache) in log_cache_get_miss() argument
89 return cache->miss; in log_cache_get_miss()
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| /Zephyr-4.2.1/tests/subsys/logging/log_cache/src/ |
| D | main.c | 61 static void cache_get(struct log_cache *cache, uintptr_t id, in cache_get() argument
64 uint32_t hit = log_cache_get_hit(cache); in cache_get()
65 uint32_t miss = log_cache_get_miss(cache); in cache_get()
68 res = log_cache_get(cache, id, buf); in cache_get()
71 zassert_equal(hit + 1, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
72 zassert_equal(miss, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
74 zassert_equal(hit, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
75 zassert_equal(miss + 1, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
91 struct log_cache cache; in ZTEST() local
105 err = log_cache_init(&cache, &config); in ZTEST()
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| /Zephyr-4.2.1/drivers/cache/ |
| D | cache_nrf.c | 45 static inline bool is_cache_busy(NRF_CACHE_Type *cache) in is_cache_busy() argument
48 return nrf_cache_busy_check(cache); in is_cache_busy()
54 static inline void wait_for_cache(NRF_CACHE_Type *cache) in wait_for_cache() argument
56 while (is_cache_busy(cache)) { in wait_for_cache()
60 static inline int _cache_all(NRF_CACHE_Type *cache, enum k_nrf_cache_op op) in _cache_all() argument
62 wait_for_cache(cache); in _cache_all()
70 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_CLEANCACHE); in _cache_all()
75 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_INVALIDATECACHE); in _cache_all()
80 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_FLUSHCACHE); in _cache_all()
88 wait_for_cache(cache); in _cache_all()
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| D | Kconfig | 5 bool "External cache controller drivers"
8 Enable support for external cache controllers drivers
16 module-str = cache
22 source "drivers/cache/Kconfig.andes"
23 source "drivers/cache/Kconfig.aspeed"
24 source "drivers/cache/Kconfig.bflb"
25 source "drivers/cache/Kconfig.nrf"
26 source "drivers/cache/Kconfig.nxp_lmem_cache"
27 source "drivers/cache/Kconfig.nxp_syscon_lpcac"
28 source "drivers/cache/Kconfig.nxp_xcache"
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| D | Kconfig.andes | 6 bool "ANDES external cache driver"
19 When L2 cache is inclusive of L1, CPU only needs to perform operations
20 on L2 cache, instead of on both L1 and L2 caches.
23 int "Andes cache driver init priority"
26 This option controls the priority of the cache initialization.
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| D | Kconfig.bflb | 5 bool "Bouffalolab L1C cache system driver"
10 This option enables the cache driver for the Bouffalolab L1C cache system
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| /Zephyr-4.2.1/scripts/tests/twister/ |
| D | test_cmakecache.py | 180 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
182 assert cache.cache_file == 'dummy/path/CMakeCache.txt'
191 item = cache._entries.popitem()
202 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
204 good_val = cache.get('DUMMY_NAME')
208 bad_val = cache.get('ANOTHER_NAME')
212 bad_val = cache.get('ANOTHER_NAME', default='No such value')
235 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt')
240 res = cache.get_list('DUMMY_NAME') if \
241 correct_get else cache.get_list('ANOTHER_NAME')
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| /Zephyr-4.2.1/dts/riscv/starfive/ |
| D | jh7110-visionfive-v2.dtsi | 39 d-cache-block-size = <64>;
40 d-cache-sets = <64>;
41 d-cache-size = <32768>;
44 i-cache-block-size = <64>;
45 i-cache-sets = <64>;
46 i-cache-size = <32768>;
50 next-level-cache = <&ccache>;
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
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| D | starfive_jh7100_beagle_v.dtsi | 24 d-cache-block-size = <64>;
25 d-cache-sets = <64>;
26 d-cache-size = <32768>;
30 i-cache-block-size = <64>;
31 i-cache-sets = <64>;
32 i-cache-size = <32768>;
36 next-level-cache = <&cachectrl>;
54 d-cache-block-size = <64>;
55 d-cache-sets = <64>;
56 d-cache-size = <32768>;
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| /Zephyr-4.2.1/tests/cmake/zephyr_get/ |
| D | CMakeLists.txt | 100 set(VARIABLE "cmake cache" CACHE INTERNAL "")
103 # CMake cache value has the highest precedence.
105 assert_equal(VARIABLE "cmake cache")
135 set(TESTCASE_VARIABLE "cmake cache" CACHE INTERNAL "")
140 IMAGE no_sysbuild "cmake cache"
189 set(VARIABLE "cmake cache" CACHE INTERNAL "")
193 assert_equal(VARIABLE "cmake cache;environment;local")
204 set(VARIABLE "cmake cache" CACHE INTERNAL "")
208 assert_equal(VARIABLE "cmake cache;local")
250 set(TESTCASE_VARIABLE "cmake cache" CACHE INTERNAL "")
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| /Zephyr-4.2.1/soc/nxp/imxrt/imxrt7xx/cm33/ |
| D | flash_clock_setup.c | 13 static void enable_xspi_cache(CACHE64_CTRL_Type *cache) in enable_xspi_cache() argument
16 cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | in enable_xspi_cache()
18 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { in enable_xspi_cache()
21 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in enable_xspi_cache()
23 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in enable_xspi_cache()
26 static void disable_xspi_cache(CACHE64_CTRL_Type *cache) in disable_xspi_cache() argument
28 cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | in disable_xspi_cache()
30 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { in disable_xspi_cache()
33 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in disable_xspi_cache()
36 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in disable_xspi_cache()
[all …]
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| /Zephyr-4.2.1/doc/hardware/cache/ |
| D | config.rst | 6 This is a high-level guide to Zephyr's cache interface and Kconfig options related to
7 cache controllers. See :ref:`cache_api` for API reference material.
9 Zephyr has different Kconfig options to control how the cache controller is
15 instruction cache. The cache controller can be in the core or can be an
16 external cache controller for which a driver is provided.
19 should be set whether we plan to support and use the cache control in Zephyr
23 options must be selected when support for data or instruction cache is
27 All the code paths related to cache control must be conditionally enabled
28 depending on these symbols. When the symbol is set the cache is considered
32 For example a platform using the data cache can enable the
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| D | guide.rst | 6 This section discusses the basics of cache coherency and under what situations a
10 data cache though there is typically also an instruction cache for systems with
11 cache support.
20 While cache coherence can be a concern for data shared between SMP cores, Zephyr
22 cores. Most applications will only need to use the cache APIs for interaction
24 different OS image. For more information on cache coherence between SMP cores,
28 cache coherency needs to be considered. Typically processor caches exist as
31 processor's cache, resulting in what appears to be corrupt data. If you are
32 moving data using DMA and the processor doesn't see the data you expect, cache
37 this defeats the purpose of having a hardware cache in the first place and
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| /Zephyr-4.2.1/soc/espressif/esp32s3/ |
| D | Kconfig | 21 prompt "Instruction cache size"
24 Instruction cache size to be set on application startup.
25 If you use 16KB instruction cache rather than 32KB instruction cache,
42 prompt "Instruction cache associated ways"
45 Instruction cache associated ways to be set on application startup.
61 prompt "Instruction cache line size"
64 Instruction cache line size to be set on application startup.
81 bool "Define instruction cache wrap mode"
83 If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
88 prompt "Data cache size"
[all …]
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| /Zephyr-4.2.1/cmake/modules/ |
| D | user_cache.cmake | 5 # Configure user cache directory.
7 # The user cache can be used for caching of data that should be persistent
11 # Only data that can be safely re-generated should be placed in this cache.
13 # Zephyr build system uses this user cache to store Zephyr compiler check
20 # - USER_CACHE_DIR: User cache directory in use.
33 set(env_suffix_LOCALAPPDATA .cache)
36 # On macOS, ~/Library/Caches is the preferred cache directory.
39 set(env_suffix_HOME .cache)
51 # that is defined and defaulting to $HOME/.cache otherwise.
83 # Zephyr's cache files go in the "zephyr" subdirectory of the
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| /Zephyr-4.2.1/soc/espressif/esp32s2/ |
| D | Kconfig | 20 prompt "Instruction cache line size"
32 prompt "Instruction cache size"
36 bool "8KB instruction cache size"
39 bool "16KB instruction cache size"
44 prompt "Data cache size"
47 Data cache size to be set on application startup.
62 prompt "Data cache line size"
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| /Zephyr-4.2.1/subsys/net/l2/ieee802154/ |
| D | ieee802154_6lo_fragment.c | 48 static struct frag_cache cache[REASS_CACHE_SIZE]; variable
264 if (!(cache[i].size == size && cache[i].tag == tag)) { in clear_reass_cache()
268 if (cache[i].pkt) { in clear_reass_cache()
269 net_pkt_unref(cache[i].pkt); in clear_reass_cache()
272 cache[i].pkt = NULL; in clear_reass_cache()
273 cache[i].size = 0U; in clear_reass_cache()
274 cache[i].tag = 0U; in clear_reass_cache()
275 cache[i].used = false; in clear_reass_cache()
276 k_work_cancel_delayable(&cache[i].timer); in clear_reass_cache()
309 if (cache[i].used) { in set_reass_cache()
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| /Zephyr-4.2.1/arch/posix/core/ |
| D | swap.c | 46 _kernel.ready_q.cache->callee_saved.thread_status; in arch_swap()
53 z_current_thread_set(_kernel.ready_q.cache); in arch_swap()
91 _kernel.ready_q.cache->callee_saved.thread_status; in arch_switch_to_main_thread()
97 z_current_thread_set(_kernel.ready_q.cache); in arch_switch_to_main_thread()
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| /Zephyr-4.2.1/doc/_extensions/zephyr/ |
| D | doxybridge.py | 135 cache = {}
148 cache.setdefault(kind, {})[name] = id
154 cache.setdefault("enumerator", {})[enumname] = enumid
156 return cache
160 cache = {}
165 cache.setdefault(kind, {}).update(data)
167 return cache
172 cache = {}
188 cache.setdefault(kind, {})[name] = id
192 cache.setdefault(kind, {}).update(data)
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| /Zephyr-4.2.1/drivers/syscon/ |
| D | syscon_bflb_efuse.c | 22 uint8_t cache[DT_INST_PROP(0, size)]; member
165 data->cache[i * sizeof(uint32_t) + 3] = (tmp & 0xFF000000U) >> 24; in efuse_bflb_cache()
166 data->cache[i * sizeof(uint32_t) + 2] = (tmp & 0x00FF0000U) >> 16; in efuse_bflb_cache()
167 data->cache[i * sizeof(uint32_t) + 1] = (tmp & 0x0000FF00U) >> 8; in efuse_bflb_cache()
168 data->cache[i * sizeof(uint32_t) + 0] = (tmp & 0x000000FFU); in efuse_bflb_cache()
190 *val = *((uint32_t *)&data->cache[reg]); in efuse_bflb_read()
206 *addr = (uintptr_t)data->cache; in efuse_bflb_get_base()
223 .cache = {0},
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| /Zephyr-4.2.1/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 27 i-cache-line-size = <32>;
28 d-cache-line-size = <32>;
46 i-cache-line-size = <32>;
47 d-cache-line-size = <32>;
65 i-cache-line-size = <32>;
66 d-cache-line-size = <32>;
84 i-cache-line-size = <32>;
85 d-cache-line-size = <32>;
103 i-cache-line-size = <32>;
104 d-cache-line-size = <32>;
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| /Zephyr-4.2.1/subsys/fs/nvs/ |
| D | Kconfig | 17 bool "Non-volatile Storage lookup cache"
19 Enable Non-volatile Storage cache, used to reduce the NVS data lookup
20 time. Each cache entry holds an address of the most recent allocation
21 table entry (ATE) for all NVS IDs that fall into that cache position.
24 int "Non-volatile Storage lookup cache size"
29 Number of entries in Non-volatile Storage lookup cache.
|
