Home
last modified time | relevance | path

Searched refs:DT_INST_REG_ADDR_BY_IDX (Results 1 – 25 of 42) sorted by relevance

12

/Zephyr-4.1.0/drivers/hwinfo/
Dhwinfo_sam0.c23 DT_INST_REG_ADDR_BY_IDX(0, 0)); in z_impl_hwinfo_get_device_id()
25 DT_INST_REG_ADDR_BY_IDX(0, 1)); in z_impl_hwinfo_get_device_id()
27 DT_INST_REG_ADDR_BY_IDX(0, 2)); in z_impl_hwinfo_get_device_id()
29 DT_INST_REG_ADDR_BY_IDX(0, 3)); in z_impl_hwinfo_get_device_id()
/Zephyr-4.1.0/drivers/interrupt_controller/
Dwuc_ite_it8xxx2.c105 .reg_wuemr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 0), \
106 .reg_wuesr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 1), \
107 .reg_wuenr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 2), \
108 .reg_wubemr = (uint8_t *) DT_INST_REG_ADDR_BY_IDX(inst, 3), \
/Zephyr-4.1.0/drivers/pwm/
Dpwm_ite_it8801.c166 .reg_mcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
167 .reg_dcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
168 .reg_prslr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
169 .reg_prsmr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
Dpwm_ite_it8xxx2.c288 .reg_dcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
289 .reg_pcssg = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
290 .reg_pcsgr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
291 .reg_pwmpol = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
/Zephyr-4.1.0/drivers/sensor/ite/ite_vcmp_it8xxx2/
Dvcmp_ite_it8xxx2.c388 .reg_vcmpxctl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
389 .reg_vcmpxcselm = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
390 .reg_vcmpscp = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 2), \
391 .reg_vcmpxthrdatm = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 3), \
392 .reg_vcmpxthrdatl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 4), \
393 .reg_vcmpsts = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 5), \
394 .reg_vcmpsts2 = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 6), \
/Zephyr-4.1.0/drivers/input/
Dinput_ite_it8801_kbd.c216 .reg_ksomcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
217 .reg_ksidr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
218 .reg_ksieer = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
219 .reg_ksiier = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
/Zephyr-4.1.0/drivers/sensor/ite/ite_tach_it8xxx2/
Dtach_ite_it8xxx2.c225 .reg_fxtlrr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
226 .reg_fxtmrr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
227 .reg_tswctlr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
/Zephyr-4.1.0/drivers/mipi_dsi/
Ddsi_mcux.c345 .host = (DSI_HOST_Type *)DT_INST_REG_ADDR_BY_IDX(id, 0), \
346 .dpi = (DSI_HOST_DPI_INTFC_Type *)DT_INST_REG_ADDR_BY_IDX(id, 1), \
347 .apb = (DSI_HOST_APB_PKT_IF_Type *)DT_INST_REG_ADDR_BY_IDX(id, 2), \
349 DT_INST_REG_ADDR_BY_IDX(id, 3), \
/Zephyr-4.1.0/drivers/counter/
Dcounter_cmos.c22 #define X86_CMOS_ADDR (DT_INST_REG_ADDR_BY_IDX(0, 0))
23 #define X86_CMOS_DATA (DT_INST_REG_ADDR_BY_IDX(0, 1))
/Zephyr-4.1.0/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c398 .reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
399 .reg_pdsc = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
410 .reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
411 .reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
/Zephyr-4.1.0/drivers/gpio/
Dgpio_ite_it8801.c449 .reg_ipsr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
450 .reg_sovr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
451 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
452 .reg_gpisr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
453 .reg_gpier = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
Dgpio_rp1.c213 .gpio_offset = DT_INST_REG_ADDR_BY_IDX(n, 0), \
214 .rio_offset = DT_INST_REG_ADDR_BY_IDX(n, 1), \
215 .pads_offset = DT_INST_REG_ADDR_BY_IDX(n, 2), \
Dgpio_ite_it8xxx2_v2.c540 .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
541 .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
542 .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
543 .reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
544 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
Dgpio_ene_kb1200.c219 .gpio_regs = (struct gpio_regs *)DT_INST_REG_ADDR_BY_IDX(n, 0), \
220 .gptd_regs = (struct gptd_regs *)DT_INST_REG_ADDR_BY_IDX(n, 1), \
Dgpio_mchp_xec_v2.c539 .pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
540 .parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
541 .parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2),\
Dgpio_ite_it8xxx2.c697 .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
698 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
699 .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
700 .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
Dgpio_mchp_mec5.c520 .pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
521 .parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
522 .parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2), \
Dgpio_sy1xx.c165 .port_base_addr = (uint32_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
/Zephyr-4.1.0/drivers/timer/
Driscv_machine_timer.c19 #define MTIME_REG DT_INST_REG_ADDR_BY_IDX(0, 0)
20 #define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
/Zephyr-4.1.0/drivers/clock_control/
Dclock_control_mchp_xec.c758 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in xec_clock_control_core_clock_divider_set()
783 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in z_mchp_xec_pcr_periph_sleep()
804 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in z_mchp_xec_pcr_periph_reset()
827 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in xec_cc_on()
997 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in mchp_xec_clk_ctrl_sys_sleep_enable()
1010 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0); in mchp_xec_clk_ctrl_sys_sleep_disable()
1073 .pcr_base = DT_INST_REG_ADDR_BY_IDX(0, 0),
1074 .vbr_base = DT_INST_REG_ADDR_BY_IDX(0, 1),
/Zephyr-4.1.0/drivers/entropy/
Dentropy_npcx_drbg.c34 #define NPCX_NCL_DRBG_BASE_ADDR ((const struct npcx_ncl_drbg *)DT_INST_REG_ADDR_BY_IDX(0, 0))
73 #define NPCX_NCL_SHA_POWER_ADDR ((const struct npcx_ncl_drbg *)DT_INST_REG_ADDR_BY_IDX(0, 1))
/Zephyr-4.1.0/drivers/fpga/
Dfpga_mpfs.c401 .base = DT_INST_REG_ADDR_BY_IDX(0, 0),
402 .mailbox = DT_INST_REG_ADDR_BY_IDX(0, 2),
/Zephyr-4.1.0/drivers/espi/
Despi_it8xxx2.c1880 .base_espi_slave = DT_INST_REG_ADDR_BY_IDX(0, 0),
1881 .base_espi_vw = DT_INST_REG_ADDR_BY_IDX(0, 1),
1882 .base_espi_queue0 = DT_INST_REG_ADDR_BY_IDX(0, 2),
1883 .base_espi_queue1 = DT_INST_REG_ADDR_BY_IDX(0, 3),
1884 .base_ec2i = DT_INST_REG_ADDR_BY_IDX(0, 4),
1885 .base_kbc = DT_INST_REG_ADDR_BY_IDX(0, 5),
1886 .base_pmc = DT_INST_REG_ADDR_BY_IDX(0, 6),
1887 .base_smfi = DT_INST_REG_ADDR_BY_IDX(0, 7),
Despi_saf_mchp_xec.c835 .saf_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 0),
836 .qmspi_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 1),
837 .saf_comm_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 2),
/Zephyr-4.1.0/drivers/rtc/
Drtc_mc146818.c19 #define RTC_STD_INDEX (DT_INST_REG_ADDR_BY_IDX(0, 0))
20 #define RTC_STD_TARGET (DT_INST_REG_ADDR_BY_IDX(0, 1))

12