Searched refs:DT_INST_PHA (Results 1 – 14 of 14) sorted by relevance
| /Zephyr-4.1.0/drivers/serial/ |
| D | uart_pl011_ambiq.h | 175 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
177 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
193 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
195 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
196 while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
197 DT_INST_PHA(n, ambiq_pwrcfg, mask)) { \
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| D | uart_ns16550.c | 1942 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
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| /Zephyr-4.1.0/drivers/spi/ |
| D | spi_ambiq_bleif.c | 203 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
204 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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| D | spi_ambiq_spid.c | 402 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
403 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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| D | spi_ambiq_spic.c | 497 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
498 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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| /Zephyr-4.1.0/drivers/clock_control/ |
| D | clock_control_nrf_auxpll.c | 131 DT_INST_PHA(n, nordic_ficrs, offset), \
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| /Zephyr-4.1.0/drivers/adc/ |
| D | adc_ambiq.c | 410 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
411 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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| /Zephyr-4.1.0/drivers/pwm/ |
| D | pwm_silabs_siwx91x.c | 227 .clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \
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| /Zephyr-4.1.0/drivers/i2c/ |
| D | i2c_ambiq.c | 428 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
429 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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| /Zephyr-4.1.0/drivers/watchdog/ |
| D | wdt_silabs_siwx91x.c | 263 .clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \
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| /Zephyr-4.1.0/drivers/gpio/ |
| D | gpio_lpc11u6x.c | 504 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(0, clocks, clkid),
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| /Zephyr-4.1.0/drivers/dma/ |
| D | dma_silabs_siwx91x.c | 451 .clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \
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| /Zephyr-4.1.0/include/zephyr/ |
| D | devicetree.h | 4369 #define DT_INST_PHA(inst, pha, cell) DT_INST_PHA_BY_IDX(inst, pha, 0, cell) macro
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| /Zephyr-4.1.0/tests/lib/devicetree/api/src/ |
| D | main.c | 1127 zassert_equal(DT_INST_PHA(0, gpios, pin), 10, ""); in ZTEST()
1128 zassert_equal(DT_INST_PHA(0, gpios, flags), 20, ""); in ZTEST()
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