Searched refs:DT_INST_CLOCKS_CTLR (Results 1 – 25 of 153) sorted by relevance
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| /Zephyr-4.1.0/drivers/clock_control/ |
| D | clock_control_wch_rcc.c | 22 #if DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_pll_clock) || \
23 DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v20x_30x_pll_clock)
25 #if DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hse_clock)
27 #elif DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hsi_clock)
30 #elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hse_clock)
32 #elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hsi_clock)
159 .mul = DT_PROP_OR(DT_INST_CLOCKS_CTLR(idx), mul, 1), \
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| D | clock_control_si32_apb.c | 75 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| D | clock_control_si32_ahb.c | 98 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| D | clock_control_nrf_auxpll.c | 129 .ref_clk_hz = DT_PROP(DT_INST_CLOCKS_CTLR(n), clock_frequency), \
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| /Zephyr-4.1.0/drivers/ethernet/eth_nxp_enet_qos/ |
| D | eth_nxp_enet_qos.c | 35 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| /Zephyr-4.1.0/drivers/serial/ |
| D | uart_realtek_rts5912.c | 61 .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| D | uart_pl011.c | 624 COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), (), \
625 (.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
706 COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(n), fixed_clock), \
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| /Zephyr-4.1.0/drivers/misc/pio_rpi_pico/ |
| D | pio_rpi_pico.c | 65 .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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| /Zephyr-4.1.0/drivers/dac/ |
| D | dac_esp32.c | 88 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
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| /Zephyr-4.1.0/drivers/entropy/ |
| D | entropy_max32.c | 83 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| /Zephyr-4.1.0/include/zephyr/devicetree/ |
| D | clocks.h | 301 #define DT_INST_CLOCKS_CTLR(inst) DT_INST_CLOCKS_CTLR_BY_IDX(inst, 0) macro
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| /Zephyr-4.1.0/drivers/pinctrl/ |
| D | pinctrl_nxp_port.c | 89 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| /Zephyr-4.1.0/drivers/timer/ |
| D | rcar_cmt_timer.c | 98 clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); in sys_clock_driver_init()
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| /Zephyr-4.1.0/drivers/mdio/ |
| D | mdio_nxp_imx_netc.c | 93 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| /Zephyr-4.1.0/drivers/spi/spi_nxp_lpspi/ |
| D | spi_nxp_lpspi_priv.h | 99 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| /Zephyr-4.1.0/drivers/gpio/ |
| D | wch_gpio_ch32v00x.c | 139 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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| /Zephyr-4.1.0/drivers/watchdog/ |
| D | xt_wdt_esp32.c | 160 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| D | wdt_mcux_wdog.c | 170 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| D | wdt_rpi_pico.c | 184 .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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| /Zephyr-4.1.0/drivers/w1/ |
| D | w1_max32.c | 195 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
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| /Zephyr-4.1.0/drivers/rtc/ |
| D | rtc_rts5912.c | 150 .clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
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| /Zephyr-4.1.0/drivers/pwm/ |
| D | pwm_mcux_qtmr.c | 165 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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| D | pwm_silabs_siwx91x.c | 226 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
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| /Zephyr-4.1.0/drivers/interrupt_controller/ |
| D | intc_rv32m1_intmux.c | 147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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| /Zephyr-4.1.0/drivers/counter/ |
| D | timer_dtmr_cmsdk_apb.c | 151 const struct device *const clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); in dtmr_cmsdk_apb_init()
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