1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Definitions for IEEE 802.3 management interface 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_NET_MDIO_H_ 13 #define ZEPHYR_INCLUDE_NET_MDIO_H_ 14 15 /** 16 * @brief Definitions for IEEE 802.3 management interface 17 * @defgroup ethernet_mdio IEEE 802.3 management interface 18 * @ingroup ethernet 19 * @{ 20 */ 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /** MDIO transaction operation code */ 27 enum mdio_opcode { 28 /** IEEE 802.3 22.2.4.5.4 write operation */ 29 MDIO_OP_C22_WRITE = 1, 30 31 /** IEEE 802.3 22.2.4.5.4 read operation */ 32 MDIO_OP_C22_READ = 2, 33 34 /** IEEE 802.3 45.3.4 address operation */ 35 MDIO_OP_C45_ADDRESS = 0, 36 37 /** IEEE 802.3 45.3.4 write operation */ 38 MDIO_OP_C45_WRITE = 1, 39 40 /** IEEE 802.3 45.3.4 post-read-increment-address operation */ 41 MDIO_OP_C45_READ_INC = 2, 42 43 /** IEEE 802.3 45.3.4 read operation */ 44 MDIO_OP_C45_READ = 3 45 }; 46 47 /* MDIO Manageable Device addresses */ 48 /** Physical Medium Attachment / Physical Medium Dependent */ 49 #define MDIO_MMD_PMAPMD 0x01U 50 /** WAN Interface Sublayer */ 51 #define MDIO_MMD_WIS 0x02U 52 /** Physical Coding Sublayer */ 53 #define MDIO_MMD_PCS 0x03U 54 /** PHY Extender Sublayer */ 55 #define MDIO_MMD_PHYXS 0x04U 56 /** DTE Extender Sublayer */ 57 #define MDIO_MMD_DTEXS 0x05U 58 /** Transmission Convergence */ 59 #define MDIO_MMD_TC 0x06U 60 /** Auto-negotiation */ 61 #define MDIO_MMD_AN 0x07U 62 /** Separated PMA (1) */ 63 #define MDIO_MMD_SEPARATED_PMA1 0x08U 64 /** Separated PMA (2) */ 65 #define MDIO_MMD_SEPARATED_PMA2 0x09U 66 /** Separated PMA (3) */ 67 #define MDIO_MMD_SEPARATED_PMA3 0x0AU 68 /** Separated PMA (4) */ 69 #define MDIO_MMD_SEPARATED_PMA4 0x0BU 70 /** Clause 22 extension */ 71 #define MDIO_MMD_C22EXT 0x1DU 72 /** Vendor Specific 1 */ 73 #define MDIO_MMD_VENDOR_SPECIFIC1 0x1EU 74 /** Vendor Specific 2 */ 75 #define MDIO_MMD_VENDOR_SPECIFIC2 0x1FU 76 77 /* MDIO generic registers */ 78 /** Control 1 */ 79 #define MDIO_CTRL1 0x0000U 80 /** Status 1 */ 81 #define MDIO_STAT1 0x0001U 82 /** Device identifier (1) */ 83 #define MDIO_DEVID1 0x0002U 84 /** Device identifier (2) */ 85 #define MDIO_DEVID2 0x0003U 86 /** Speed ability */ 87 #define MDIO_SPEED 0x0004U 88 /** Devices in package (1) */ 89 #define MDIO_DEVS1 0x0005U 90 /** Devices in package (2) */ 91 #define MDIO_DEVS2 0x0006U 92 /** Control 2 */ 93 #define MDIO_CTRL2 0x0007U 94 /** Status 2 */ 95 #define MDIO_STAT2 0x0008U 96 /** Package identifier (1) */ 97 #define MDIO_PKGID1 0x000EU 98 /** Package identifier (2) */ 99 #define MDIO_PKGID2 0x000FU 100 101 102 /* BASE-T1 registers */ 103 /** BASE-T1 Auto-negotiation control */ 104 #define MDIO_AN_T1_CTRL 0x0200U 105 /** BASE-T1 Auto-negotiation status */ 106 #define MDIO_AN_T1_STAT 0x0201U 107 /** BASE-T1 Auto-negotiation advertisement register [15:0] */ 108 #define MDIO_AN_T1_ADV_L 0x0202U 109 /** BASE-T1 Auto-negotiation advertisement register [31:16] */ 110 #define MDIO_AN_T1_ADV_M 0x0203U 111 /** BASE-T1 Auto-negotiation advertisement register [47:32] */ 112 #define MDIO_AN_T1_ADV_H 0x0204U 113 /* BASE-T1 PMA/PMD control register */ 114 #define MDIO_PMA_PMD_BT1_CTRL 0x0834U 115 116 /* BASE-T1 Auto-negotiation Control register */ 117 /** Auto-negotiation Restart */ 118 #define MDIO_AN_T1_CTRL_RESTART BIT(9) 119 /** Auto-negotiation Enable */ 120 #define MDIO_AN_T1_CTRL_EN BIT(12) 121 122 /* BASE-T1 Auto-negotiation Status register */ 123 /** Link Status */ 124 #define MDIO_AN_T1_STAT_LINK_STATUS BIT(2) 125 /** Auto-negotiation Ability */ 126 #define MDIO_AN_T1_STAT_ABLE BIT(3) 127 /** Auto-negotiation Remote Fault */ 128 #define MDIO_AN_T1_STAT_REMOTE_FAULT BIT(4) 129 /** Auto-negotiation Complete */ 130 #define MDIO_AN_T1_STAT_COMPLETE BIT(5) 131 /** Page Received */ 132 #define MDIO_AN_T1_STAT_PAGE_RX BIT(6) 133 134 /* BASE-T1 Auto-negotiation Advertisement register [15:0] */ 135 /** Pause Ability */ 136 #define MDIO_AN_T1_ADV_L_PAUSE_CAP BIT(10) 137 /** Pause Ability */ 138 #define MDIO_AN_T1_ADV_L_PAUSE_ASYM BIT(11) 139 /** Force Master/Slave Configuration */ 140 #define MDIO_AN_T1_ADV_L_FORCE_MS BIT(12) 141 /** Remote Fault */ 142 #define MDIO_AN_T1_ADV_L_REMOTE_FAULT BIT(13) 143 /** Acknowledge (ACK) */ 144 #define MDIO_AN_T1_ADV_L_ACK BIT(14) 145 /** Next Page Request */ 146 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ BIT(15) 147 148 /* BASE-T1 Auto-negotiation Advertisement register [31:16] */ 149 /** 10BASE-T1L Ability */ 150 #define MDIO_AN_T1_ADV_M_B10L BIT(14) 151 /** Master/slave Configuration */ 152 #define MDIO_AN_T1_ADV_M_MST BIT(4) 153 154 /* BASE-T1 Auto-negotiation Advertisement register [47:32] */ 155 /* 10BASE-T1L High Level Transmit Operating Mode Request */ 156 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ BIT(12) 157 /* 10BASE-T1L High Level Transmit Operating Mode Ability */ 158 #define MDIO_AN_T1_ADV_H_10L_TX_HI BIT(13) 159 160 /* BASE-T1 PMA/PMD control register */ 161 /** BASE-T1 master/slave configuration */ 162 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST BIT(14) 163 164 165 /* 10BASE-T1L registers */ 166 /** 10BASE-T1L PMA control */ 167 #define MDIO_PMA_B10L_CTRL 0x08F6U 168 /** 10BASE-T1L PMA status */ 169 #define MDIO_PMA_B10L_STAT 0x08F7U 170 /** 10BASE-T1L PMA link status*/ 171 #define MDIO_PMA_B10L_LINK_STAT 0x8302U 172 /** 10BASE-T1L PCS control */ 173 #define MDIO_PCS_B10L_CTRL 0x08E6U 174 /** 10BASE-T1L PCS status */ 175 #define MDIO_PCS_B10L_STAT 0x08E7U 176 177 /* 10BASE-T1L PMA control register */ 178 /** 10BASE-T1L Transmit Disable Mode */ 179 #define MDIO_PMA_B10L_CTRL_TX_DIS_MODE_EN BIT(14) 180 /** 10BASE-T1L Transmit Voltage Amplitude Control */ 181 #define MDIO_PMA_B10L_CTRL_TX_LVL_HI BIT(12) 182 /** 10BASE-T1L EEE Enable */ 183 #define MDIO_PMA_B10L_CTRL_EEE BIT(10) 184 /** 10BASE-T1L PMA Loopback */ 185 #define MDIO_PMA_B10L_CTRL_LB_PMA_LOC_EN BIT(0) 186 187 /* 10BASE-T1L PMA status register */ 188 /** 10BASE-T1L PMA receive link up */ 189 #define MDIO_PMA_B10L_STAT_LINK BIT(0) 190 /** 10BASE-T1L Fault condition detected */ 191 #define MDIO_PMA_B10L_STAT_FAULT BIT(1) 192 /** 10BASE-T1L Receive polarity is reversed */ 193 #define MDIO_PMA_B10L_STAT_POLARITY BIT(2) 194 /** 10BASE-T1L Able to detect fault on receive path */ 195 #define MDIO_PMA_B10L_STAT_RECV_FAULT BIT(9) 196 /** 10BASE-T1L PHY has EEE ability */ 197 #define MDIO_PMA_B10L_STAT_EEE BIT(10) 198 /** 10BASE-T1L PMA has low-power ability */ 199 #define MDIO_PMA_B10L_STAT_LOW_POWER BIT(11) 200 /** 10BASE-T1L PHY has 2.4 Vpp operating mode ability */ 201 #define MDIO_PMA_B10L_STAT_2V4_ABLE BIT(12) 202 /** 10BASE-T1L PHY has loopback ability */ 203 #define MDIO_PMA_B10L_STAT_LB_ABLE BIT(13) 204 205 /* 10BASE-T1L PMA link status*/ 206 /** 10BASE-T1L Remote Receiver Status OK Latch Low */ 207 #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK_LL BIT(9) 208 /** 10BASE-T1L Remote Receiver Status OK */ 209 #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK BIT(8) 210 /** 10BASE-T1L Local Receiver Status OK */ 211 #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK_LL BIT(7) 212 /** 10BASE-T1L Local Receiver Status OK */ 213 #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK BIT(6) 214 /** 10BASE-T1L Descrambler Status OK Latch Low */ 215 #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK_LL BIT(5) 216 /** 10BASE-T1L Descrambler Status OK */ 217 #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK BIT(4) 218 /** 10BASE-T1L Link Status OK Latch Low */ 219 #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK_LL BIT(1) 220 /** 10BASE-T1L Link Status OK */ 221 #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK BIT(0) 222 223 /* 10BASE-T1L PCS control */ 224 /** 10BASE-T1L PCS Loopback Enable */ 225 #define MDIO_PCS_B10L_CTRL_LB_PCS_EN BIT(14) 226 227 /* 10BASE-T1L PCS status */ 228 /** 10BASE-T1L PCS Descrambler Status */ 229 #define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL BIT(2) 230 231 #ifdef __cplusplus 232 } 233 #endif 234 235 /** 236 * @} 237 */ 238 239 #endif /* ZEPHYR_INCLUDE_NET_MDIO_H_ */ 240
