1 /* 2 * Copyright (c) 2022 Google Inc 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ 9 10 #include "stm32-common.h" 11 12 /* RCC bus reset register offset */ 13 #define STM32_RESET_BUS_AHB1 0x28 14 #define STM32_RESET_BUS_AHB2 0x2C 15 #define STM32_RESET_BUS_AHB3 0x30 16 #define STM32_RESET_BUS_APB1L 0x38 17 #define STM32_RESET_BUS_APB1H 0x3C 18 #define STM32_RESET_BUS_APB2 0x40 19 20 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_ */ 21
