1 /*
2  * Copyright (c) 2022 Teslabs Engineering S.L.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
9 
10 #include "gd32-common.h"
11 
12 /**
13  * @name Register offsets
14  * @{
15  */
16 
17 #define GD32_APB2RST_OFFSET       0x0CU
18 #define GD32_APB1RST_OFFSET       0x10U
19 #define GD32_AHBRST_OFFSET        0x28U
20 #define GD32_ADDAPB1RST_OFFSET    0xE0U
21 
22 /** @} */
23 
24 /**
25  * @name Clock enable/disable definitions for peripherals
26  * @{
27  */
28 
29 /* APB2 peripherals */
30 #define GD32_RESET_AFIO       GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA      GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB      GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC      GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD      GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE      GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF      GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG      GD32_RESET_CONFIG(APB2RST, 8U)
38 #define GD32_RESET_ADC0       GD32_RESET_CONFIG(APB2RST, 9U)
39 #define GD32_RESET_ADC1       GD32_RESET_CONFIG(APB2RST, 10U)
40 #define GD32_RESET_TIMER0     GD32_RESET_CONFIG(APB2RST, 11U)
41 #define GD32_RESET_SPI0       GD32_RESET_CONFIG(APB2RST, 12U)
42 #define GD32_RESET_TIMER7     GD32_RESET_CONFIG(APB2RST, 13U)
43 #define GD32_RESET_USART0     GD32_RESET_CONFIG(APB2RST, 14U)
44 #define GD32_RESET_ADC2       GD32_RESET_CONFIG(APB2RST, 15U)
45 #define GD32_RESET_TIMER8     GD32_RESET_CONFIG(APB2RST, 19U)
46 #define GD32_RESET_TIMER9     GD32_RESET_CONFIG(APB2RST, 20U)
47 #define GD32_RESET_TIMER10    GD32_RESET_CONFIG(APB2RST, 21U)
48 
49 /* APB1 peripherals */
50 #define GD32_RESET_TIMER2     GD32_RESET_CONFIG(APB1RST, 1U)
51 #define GD32_RESET_TIMER3     GD32_RESET_CONFIG(APB1RST, 2U)
52 #define GD32_RESET_TIMER5     GD32_RESET_CONFIG(APB1RST, 4U)
53 #define GD32_RESET_TIMER6     GD32_RESET_CONFIG(APB1RST, 5U)
54 #define GD32_RESET_TIMER11    GD32_RESET_CONFIG(APB1RST, 6U)
55 #define GD32_RESET_TIMER12    GD32_RESET_CONFIG(APB1RST, 7U)
56 #define GD32_RESET_TIMER13    GD32_RESET_CONFIG(APB1RST, 8U)
57 #define GD32_RESET_WWDGT      GD32_RESET_CONFIG(APB1RST, 11U)
58 #define GD32_RESET_SPI1       GD32_RESET_CONFIG(APB1RST, 14U)
59 #define GD32_RESET_SPI2       GD32_RESET_CONFIG(APB1RST, 15U)
60 #define GD32_RESET_USART1     GD32_RESET_CONFIG(APB1RST, 17U)
61 #define GD32_RESET_USART2     GD32_RESET_CONFIG(APB1RST, 18U)
62 #define GD32_RESET_UART3      GD32_RESET_CONFIG(APB1RST, 19U)
63 #define GD32_RESET_UART4      GD32_RESET_CONFIG(APB1RST, 20U)
64 #define GD32_RESET_I2C0       GD32_RESET_CONFIG(APB1RST, 21U)
65 #define GD32_RESET_I2C1       GD32_RESET_CONFIG(APB1RST, 22U)
66 #define GD32_RESET_CAN0       GD32_RESET_CONFIG(APB1RST, 25U)
67 #define GD32_RESET_CAN1       GD32_RESET_CONFIG(APB1RST, 26U)
68 #define GD32_RESET_BKPI       GD32_RESET_CONFIG(APB1RST, 27U)
69 #define GD32_RESET_PMU        GD32_RESET_CONFIG(APB1RST, 28U)
70 #define GD32_RESET_DAC        GD32_RESET_CONFIG(APB1RST, 29U)
71 
72 /* AHB peripherals */
73 #define GD32_RESET_USBFS      GD32_RESET_CONFIG(AHBRST, 12U)
74 
75 /* APB1 additional peripherals */
76 #define GD32_RESET_CTC        GD32_RESET_CONFIG(ADDAPB1RST, 27U)
77 
78 /** @} */
79 
80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_ */
81