1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ 9 10 #define IMX_SC_R_A53 0U 11 #define IMX_SC_R_A53_0 1U 12 #define IMX_SC_R_A53_1 2U 13 #define IMX_SC_R_A53_2 3U 14 #define IMX_SC_R_A53_3 4U 15 #define IMX_SC_R_A72 5U 16 #define IMX_SC_R_A72_0 6U 17 #define IMX_SC_R_A72_1 7U 18 #define IMX_SC_R_A72_2 8U 19 #define IMX_SC_R_A72_3 9U 20 #define IMX_SC_R_CCI 10U 21 #define IMX_SC_R_DB 11U 22 #define IMX_SC_R_DRC_0 12U 23 #define IMX_SC_R_DRC_1 13U 24 #define IMX_SC_R_GIC_SMMU 14U 25 #define IMX_SC_R_IRQSTR_M4_0 15U 26 #define IMX_SC_R_IRQSTR_M4_1 16U 27 #define IMX_SC_R_SMMU 17U 28 #define IMX_SC_R_GIC 18U 29 #define IMX_SC_R_DC_0_BLIT0 19U 30 #define IMX_SC_R_DC_0_BLIT1 20U 31 #define IMX_SC_R_DC_0_BLIT2 21U 32 #define IMX_SC_R_DC_0_BLIT_OUT 22U 33 #define IMX_SC_R_PERF 23U 34 #define IMX_SC_R_USB_1_PHY 24U 35 #define IMX_SC_R_DC_0_WARP 25U 36 #define IMX_SC_R_V2X_MU_0 26U 37 #define IMX_SC_R_V2X_MU_1 27U 38 #define IMX_SC_R_DC_0_VIDEO0 28U 39 #define IMX_SC_R_DC_0_VIDEO1 29U 40 #define IMX_SC_R_DC_0_FRAC0 30U 41 #define IMX_SC_R_V2X_MU_2 31U 42 #define IMX_SC_R_DC_0 32U 43 #define IMX_SC_R_GPU_2_PID0 33U 44 #define IMX_SC_R_DC_0_PLL_0 34U 45 #define IMX_SC_R_DC_0_PLL_1 35U 46 #define IMX_SC_R_DC_1_BLIT0 36U 47 #define IMX_SC_R_DC_1_BLIT1 37U 48 #define IMX_SC_R_DC_1_BLIT2 38U 49 #define IMX_SC_R_DC_1_BLIT_OUT 39U 50 #define IMX_SC_R_V2X_MU_3 40U 51 #define IMX_SC_R_V2X_MU_4 41U 52 #define IMX_SC_R_DC_1_WARP 42U 53 #define IMX_SC_R_UNUSED1 43U 54 #define IMX_SC_R_SECVIO 44U 55 #define IMX_SC_R_DC_1_VIDEO0 45U 56 #define IMX_SC_R_DC_1_VIDEO1 46U 57 #define IMX_SC_R_DC_1_FRAC0 47U 58 #define IMX_SC_R_UNUSED13 48U 59 #define IMX_SC_R_DC_1 49U 60 #define IMX_SC_R_UNUSED14 50U 61 #define IMX_SC_R_DC_1_PLL_0 51U 62 #define IMX_SC_R_DC_1_PLL_1 52U 63 #define IMX_SC_R_SPI_0 53U 64 #define IMX_SC_R_SPI_1 54U 65 #define IMX_SC_R_SPI_2 55U 66 #define IMX_SC_R_SPI_3 56U 67 #define IMX_SC_R_UART_0 57U 68 #define IMX_SC_R_UART_1 58U 69 #define IMX_SC_R_UART_2 59U 70 #define IMX_SC_R_UART_3 60U 71 #define IMX_SC_R_UART_4 61U 72 #define IMX_SC_R_EMVSIM_0 62U 73 #define IMX_SC_R_EMVSIM_1 63U 74 #define IMX_SC_R_DMA_0_CH0 64U 75 #define IMX_SC_R_DMA_0_CH1 65U 76 #define IMX_SC_R_DMA_0_CH2 66U 77 #define IMX_SC_R_DMA_0_CH3 67U 78 #define IMX_SC_R_DMA_0_CH4 68U 79 #define IMX_SC_R_DMA_0_CH5 69U 80 #define IMX_SC_R_DMA_0_CH6 70U 81 #define IMX_SC_R_DMA_0_CH7 71U 82 #define IMX_SC_R_DMA_0_CH8 72U 83 #define IMX_SC_R_DMA_0_CH9 73U 84 #define IMX_SC_R_DMA_0_CH10 74U 85 #define IMX_SC_R_DMA_0_CH11 75U 86 #define IMX_SC_R_DMA_0_CH12 76U 87 #define IMX_SC_R_DMA_0_CH13 77U 88 #define IMX_SC_R_DMA_0_CH14 78U 89 #define IMX_SC_R_DMA_0_CH15 79U 90 #define IMX_SC_R_DMA_0_CH16 80U 91 #define IMX_SC_R_DMA_0_CH17 81U 92 #define IMX_SC_R_DMA_0_CH18 82U 93 #define IMX_SC_R_DMA_0_CH19 83U 94 #define IMX_SC_R_DMA_0_CH20 84U 95 #define IMX_SC_R_DMA_0_CH21 85U 96 #define IMX_SC_R_DMA_0_CH22 86U 97 #define IMX_SC_R_DMA_0_CH23 87U 98 #define IMX_SC_R_DMA_0_CH24 88U 99 #define IMX_SC_R_DMA_0_CH25 89U 100 #define IMX_SC_R_DMA_0_CH26 90U 101 #define IMX_SC_R_DMA_0_CH27 91U 102 #define IMX_SC_R_DMA_0_CH28 92U 103 #define IMX_SC_R_DMA_0_CH29 93U 104 #define IMX_SC_R_DMA_0_CH30 94U 105 #define IMX_SC_R_DMA_0_CH31 95U 106 #define IMX_SC_R_I2C_0 96U 107 #define IMX_SC_R_I2C_1 97U 108 #define IMX_SC_R_I2C_2 98U 109 #define IMX_SC_R_I2C_3 99U 110 #define IMX_SC_R_I2C_4 100U 111 #define IMX_SC_R_ADC_0 101U 112 #define IMX_SC_R_ADC_1 102U 113 #define IMX_SC_R_FTM_0 103U 114 #define IMX_SC_R_FTM_1 104U 115 #define IMX_SC_R_CAN_0 105U 116 #define IMX_SC_R_CAN_1 106U 117 #define IMX_SC_R_CAN_2 107U 118 #define IMX_SC_R_DMA_1_CH0 108U 119 #define IMX_SC_R_DMA_1_CH1 109U 120 #define IMX_SC_R_DMA_1_CH2 110U 121 #define IMX_SC_R_DMA_1_CH3 111U 122 #define IMX_SC_R_DMA_1_CH4 112U 123 #define IMX_SC_R_DMA_1_CH5 113U 124 #define IMX_SC_R_DMA_1_CH6 114U 125 #define IMX_SC_R_DMA_1_CH7 115U 126 #define IMX_SC_R_DMA_1_CH8 116U 127 #define IMX_SC_R_DMA_1_CH9 117U 128 #define IMX_SC_R_DMA_1_CH10 118U 129 #define IMX_SC_R_DMA_1_CH11 119U 130 #define IMX_SC_R_DMA_1_CH12 120U 131 #define IMX_SC_R_DMA_1_CH13 121U 132 #define IMX_SC_R_DMA_1_CH14 122U 133 #define IMX_SC_R_DMA_1_CH15 123U 134 #define IMX_SC_R_DMA_1_CH16 124U 135 #define IMX_SC_R_DMA_1_CH17 125U 136 #define IMX_SC_R_DMA_1_CH18 126U 137 #define IMX_SC_R_DMA_1_CH19 127U 138 #define IMX_SC_R_DMA_1_CH20 128U 139 #define IMX_SC_R_DMA_1_CH21 129U 140 #define IMX_SC_R_DMA_1_CH22 130U 141 #define IMX_SC_R_DMA_1_CH23 131U 142 #define IMX_SC_R_DMA_1_CH24 132U 143 #define IMX_SC_R_DMA_1_CH25 133U 144 #define IMX_SC_R_DMA_1_CH26 134U 145 #define IMX_SC_R_DMA_1_CH27 135U 146 #define IMX_SC_R_DMA_1_CH28 136U 147 #define IMX_SC_R_DMA_1_CH29 137U 148 #define IMX_SC_R_DMA_1_CH30 138U 149 #define IMX_SC_R_DMA_1_CH31 139U 150 #define IMX_SC_R_V2X_PID0 140U 151 #define IMX_SC_R_V2X_PID1 141U 152 #define IMX_SC_R_V2X_PID2 142U 153 #define IMX_SC_R_V2X_PID3 143U 154 #define IMX_SC_R_GPU_0_PID0 144U 155 #define IMX_SC_R_GPU_0_PID1 145U 156 #define IMX_SC_R_GPU_0_PID2 146U 157 #define IMX_SC_R_GPU_0_PID3 147U 158 #define IMX_SC_R_GPU_1_PID0 148U 159 #define IMX_SC_R_GPU_1_PID1 149U 160 #define IMX_SC_R_GPU_1_PID2 150U 161 #define IMX_SC_R_GPU_1_PID3 151U 162 #define IMX_SC_R_PCIE_A 152U 163 #define IMX_SC_R_SERDES_0 153U 164 #define IMX_SC_R_MATCH_0 154U 165 #define IMX_SC_R_MATCH_1 155U 166 #define IMX_SC_R_MATCH_2 156U 167 #define IMX_SC_R_MATCH_3 157U 168 #define IMX_SC_R_MATCH_4 158U 169 #define IMX_SC_R_MATCH_5 159U 170 #define IMX_SC_R_MATCH_6 160U 171 #define IMX_SC_R_MATCH_7 161U 172 #define IMX_SC_R_MATCH_8 162U 173 #define IMX_SC_R_MATCH_9 163U 174 #define IMX_SC_R_MATCH_10 164U 175 #define IMX_SC_R_MATCH_11 165U 176 #define IMX_SC_R_MATCH_12 166U 177 #define IMX_SC_R_MATCH_13 167U 178 #define IMX_SC_R_MATCH_14 168U 179 #define IMX_SC_R_PCIE_B 169U 180 #define IMX_SC_R_SATA_0 170U 181 #define IMX_SC_R_SERDES_1 171U 182 #define IMX_SC_R_HSIO_GPIO 172U 183 #define IMX_SC_R_MATCH_15 173U 184 #define IMX_SC_R_MATCH_16 174U 185 #define IMX_SC_R_MATCH_17 175U 186 #define IMX_SC_R_MATCH_18 176U 187 #define IMX_SC_R_MATCH_19 177U 188 #define IMX_SC_R_MATCH_20 178U 189 #define IMX_SC_R_MATCH_21 179U 190 #define IMX_SC_R_MATCH_22 180U 191 #define IMX_SC_R_MATCH_23 181U 192 #define IMX_SC_R_MATCH_24 182U 193 #define IMX_SC_R_MATCH_25 183U 194 #define IMX_SC_R_MATCH_26 184U 195 #define IMX_SC_R_MATCH_27 185U 196 #define IMX_SC_R_MATCH_28 186U 197 #define IMX_SC_R_LCD_0 187U 198 #define IMX_SC_R_LCD_0_PWM_0 188U 199 #define IMX_SC_R_LCD_0_I2C_0 189U 200 #define IMX_SC_R_LCD_0_I2C_1 190U 201 #define IMX_SC_R_PWM_0 191U 202 #define IMX_SC_R_PWM_1 192U 203 #define IMX_SC_R_PWM_2 193U 204 #define IMX_SC_R_PWM_3 194U 205 #define IMX_SC_R_PWM_4 195U 206 #define IMX_SC_R_PWM_5 196U 207 #define IMX_SC_R_PWM_6 197U 208 #define IMX_SC_R_PWM_7 198U 209 #define IMX_SC_R_GPIO_0 199U 210 #define IMX_SC_R_GPIO_1 200U 211 #define IMX_SC_R_GPIO_2 201U 212 #define IMX_SC_R_GPIO_3 202U 213 #define IMX_SC_R_GPIO_4 203U 214 #define IMX_SC_R_GPIO_5 204U 215 #define IMX_SC_R_GPIO_6 205U 216 #define IMX_SC_R_GPIO_7 206U 217 #define IMX_SC_R_GPT_0 207U 218 #define IMX_SC_R_GPT_1 208U 219 #define IMX_SC_R_GPT_2 209U 220 #define IMX_SC_R_GPT_3 210U 221 #define IMX_SC_R_GPT_4 211U 222 #define IMX_SC_R_KPP 212U 223 #define IMX_SC_R_MU_0A 213U 224 #define IMX_SC_R_MU_1A 214U 225 #define IMX_SC_R_MU_2A 215U 226 #define IMX_SC_R_MU_3A 216U 227 #define IMX_SC_R_MU_4A 217U 228 #define IMX_SC_R_MU_5A 218U 229 #define IMX_SC_R_MU_6A 219U 230 #define IMX_SC_R_MU_7A 220U 231 #define IMX_SC_R_MU_8A 221U 232 #define IMX_SC_R_MU_9A 222U 233 #define IMX_SC_R_MU_10A 223U 234 #define IMX_SC_R_MU_11A 224U 235 #define IMX_SC_R_MU_12A 225U 236 #define IMX_SC_R_MU_13A 226U 237 #define IMX_SC_R_MU_5B 227U 238 #define IMX_SC_R_MU_6B 228U 239 #define IMX_SC_R_MU_7B 229U 240 #define IMX_SC_R_MU_8B 230U 241 #define IMX_SC_R_MU_9B 231U 242 #define IMX_SC_R_MU_10B 232U 243 #define IMX_SC_R_MU_11B 233U 244 #define IMX_SC_R_MU_12B 234U 245 #define IMX_SC_R_MU_13B 235U 246 #define IMX_SC_R_ROM_0 236U 247 #define IMX_SC_R_FSPI_0 237U 248 #define IMX_SC_R_FSPI_1 238U 249 #define IMX_SC_R_IEE 239U 250 #define IMX_SC_R_IEE_R0 240U 251 #define IMX_SC_R_IEE_R1 241U 252 #define IMX_SC_R_IEE_R2 242U 253 #define IMX_SC_R_IEE_R3 243U 254 #define IMX_SC_R_IEE_R4 244U 255 #define IMX_SC_R_IEE_R5 245U 256 #define IMX_SC_R_IEE_R6 246U 257 #define IMX_SC_R_IEE_R7 247U 258 #define IMX_SC_R_SDHC_0 248U 259 #define IMX_SC_R_SDHC_1 249U 260 #define IMX_SC_R_SDHC_2 250U 261 #define IMX_SC_R_ENET_0 251U 262 #define IMX_SC_R_ENET_1 252U 263 #define IMX_SC_R_MLB_0 253U 264 #define IMX_SC_R_DMA_2_CH0 254U 265 #define IMX_SC_R_DMA_2_CH1 255U 266 #define IMX_SC_R_DMA_2_CH2 256U 267 #define IMX_SC_R_DMA_2_CH3 257U 268 #define IMX_SC_R_DMA_2_CH4 258U 269 #define IMX_SC_R_USB_0 259U 270 #define IMX_SC_R_USB_1 260U 271 #define IMX_SC_R_USB_0_PHY 261U 272 #define IMX_SC_R_USB_2 262U 273 #define IMX_SC_R_USB_2_PHY 263U 274 #define IMX_SC_R_DTCP 264U 275 #define IMX_SC_R_NAND 265U 276 #define IMX_SC_R_LVDS_0 266U 277 #define IMX_SC_R_LVDS_0_PWM_0 267U 278 #define IMX_SC_R_LVDS_0_I2C_0 268U 279 #define IMX_SC_R_LVDS_0_I2C_1 269U 280 #define IMX_SC_R_LVDS_1 270U 281 #define IMX_SC_R_LVDS_1_PWM_0 271U 282 #define IMX_SC_R_LVDS_1_I2C_0 272U 283 #define IMX_SC_R_LVDS_1_I2C_1 273U 284 #define IMX_SC_R_LVDS_2 274U 285 #define IMX_SC_R_LVDS_2_PWM_0 275U 286 #define IMX_SC_R_LVDS_2_I2C_0 276U 287 #define IMX_SC_R_LVDS_2_I2C_1 277U 288 #define IMX_SC_R_M4_0_PID0 278U 289 #define IMX_SC_R_M4_0_PID1 279U 290 #define IMX_SC_R_M4_0_PID2 280U 291 #define IMX_SC_R_M4_0_PID3 281U 292 #define IMX_SC_R_M4_0_PID4 282U 293 #define IMX_SC_R_M4_0_RGPIO 283U 294 #define IMX_SC_R_M4_0_SEMA42 284U 295 #define IMX_SC_R_M4_0_TPM 285U 296 #define IMX_SC_R_M4_0_PIT 286U 297 #define IMX_SC_R_M4_0_UART 287U 298 #define IMX_SC_R_M4_0_I2C 288U 299 #define IMX_SC_R_M4_0_INTMUX 289U 300 #define IMX_SC_R_ENET_0_A0 290U 301 #define IMX_SC_R_ENET_0_A1 291U 302 #define IMX_SC_R_M4_0_MU_0B 292U 303 #define IMX_SC_R_M4_0_MU_0A0 293U 304 #define IMX_SC_R_M4_0_MU_0A1 294U 305 #define IMX_SC_R_M4_0_MU_0A2 295U 306 #define IMX_SC_R_M4_0_MU_0A3 296U 307 #define IMX_SC_R_M4_0_MU_1A 297U 308 #define IMX_SC_R_M4_1_PID0 298U 309 #define IMX_SC_R_M4_1_PID1 299U 310 #define IMX_SC_R_M4_1_PID2 300U 311 #define IMX_SC_R_M4_1_PID3 301U 312 #define IMX_SC_R_M4_1_PID4 302U 313 #define IMX_SC_R_M4_1_RGPIO 303U 314 #define IMX_SC_R_M4_1_SEMA42 304U 315 #define IMX_SC_R_M4_1_TPM 305U 316 #define IMX_SC_R_M4_1_PIT 306U 317 #define IMX_SC_R_M4_1_UART 307U 318 #define IMX_SC_R_M4_1_I2C 308U 319 #define IMX_SC_R_M4_1_INTMUX 309U 320 #define IMX_SC_R_UNUSED17 310U 321 #define IMX_SC_R_UNUSED18 311U 322 #define IMX_SC_R_M4_1_MU_0B 312U 323 #define IMX_SC_R_M4_1_MU_0A0 313U 324 #define IMX_SC_R_M4_1_MU_0A1 314U 325 #define IMX_SC_R_M4_1_MU_0A2 315U 326 #define IMX_SC_R_M4_1_MU_0A3 316U 327 #define IMX_SC_R_M4_1_MU_1A 317U 328 #define IMX_SC_R_SAI_0 318U 329 #define IMX_SC_R_SAI_1 319U 330 #define IMX_SC_R_SAI_2 320U 331 #define IMX_SC_R_IRQSTR_SCU2 321U 332 #define IMX_SC_R_IRQSTR_DSP 322U 333 #define IMX_SC_R_ELCDIF_PLL 323U 334 #define IMX_SC_R_OCRAM 324U 335 #define IMX_SC_R_AUDIO_PLL_0 325U 336 #define IMX_SC_R_PI_0 326U 337 #define IMX_SC_R_PI_0_PWM_0 327U 338 #define IMX_SC_R_PI_0_PWM_1 328U 339 #define IMX_SC_R_PI_0_I2C_0 329U 340 #define IMX_SC_R_PI_0_PLL 330U 341 #define IMX_SC_R_PI_1 331U 342 #define IMX_SC_R_PI_1_PWM_0 332U 343 #define IMX_SC_R_PI_1_PWM_1 333U 344 #define IMX_SC_R_PI_1_I2C_0 334U 345 #define IMX_SC_R_PI_1_PLL 335U 346 #define IMX_SC_R_SC_PID0 336U 347 #define IMX_SC_R_SC_PID1 337U 348 #define IMX_SC_R_SC_PID2 338U 349 #define IMX_SC_R_SC_PID3 339U 350 #define IMX_SC_R_SC_PID4 340U 351 #define IMX_SC_R_SC_SEMA42 341U 352 #define IMX_SC_R_SC_TPM 342U 353 #define IMX_SC_R_SC_PIT 343U 354 #define IMX_SC_R_SC_UART 344U 355 #define IMX_SC_R_SC_I2C 345U 356 #define IMX_SC_R_SC_MU_0B 346U 357 #define IMX_SC_R_SC_MU_0A0 347U 358 #define IMX_SC_R_SC_MU_0A1 348U 359 #define IMX_SC_R_SC_MU_0A2 349U 360 #define IMX_SC_R_SC_MU_0A3 350U 361 #define IMX_SC_R_SC_MU_1A 351U 362 #define IMX_SC_R_SYSCNT_RD 352U 363 #define IMX_SC_R_SYSCNT_CMP 353U 364 #define IMX_SC_R_DEBUG 354U 365 #define IMX_SC_R_SYSTEM 355U 366 #define IMX_SC_R_SNVS 356U 367 #define IMX_SC_R_OTP 357U 368 #define IMX_SC_R_VPU_PID0 358U 369 #define IMX_SC_R_VPU_PID1 359U 370 #define IMX_SC_R_VPU_PID2 360U 371 #define IMX_SC_R_VPU_PID3 361U 372 #define IMX_SC_R_VPU_PID4 362U 373 #define IMX_SC_R_VPU_PID5 363U 374 #define IMX_SC_R_VPU_PID6 364U 375 #define IMX_SC_R_VPU_PID7 365U 376 #define IMX_SC_R_ENET_0_A2 366U 377 #define IMX_SC_R_ENET_1_A0 367U 378 #define IMX_SC_R_ENET_1_A1 368U 379 #define IMX_SC_R_ENET_1_A2 369U 380 #define IMX_SC_R_ENET_1_A3 370U 381 #define IMX_SC_R_ENET_1_A4 371U 382 #define IMX_SC_R_DMA_4_CH0 372U 383 #define IMX_SC_R_DMA_4_CH1 373U 384 #define IMX_SC_R_DMA_4_CH2 374U 385 #define IMX_SC_R_DMA_4_CH3 375U 386 #define IMX_SC_R_DMA_4_CH4 376U 387 #define IMX_SC_R_ISI_CH0 377U 388 #define IMX_SC_R_ISI_CH1 378U 389 #define IMX_SC_R_ISI_CH2 379U 390 #define IMX_SC_R_ISI_CH3 380U 391 #define IMX_SC_R_ISI_CH4 381U 392 #define IMX_SC_R_ISI_CH5 382U 393 #define IMX_SC_R_ISI_CH6 383U 394 #define IMX_SC_R_ISI_CH7 384U 395 #define IMX_SC_R_MJPEG_DEC_S0 385U 396 #define IMX_SC_R_MJPEG_DEC_S1 386U 397 #define IMX_SC_R_MJPEG_DEC_S2 387U 398 #define IMX_SC_R_MJPEG_DEC_S3 388U 399 #define IMX_SC_R_MJPEG_ENC_S0 389U 400 #define IMX_SC_R_MJPEG_ENC_S1 390U 401 #define IMX_SC_R_MJPEG_ENC_S2 391U 402 #define IMX_SC_R_MJPEG_ENC_S3 392U 403 #define IMX_SC_R_MIPI_0 393U 404 #define IMX_SC_R_MIPI_0_PWM_0 394U 405 #define IMX_SC_R_MIPI_0_I2C_0 395U 406 #define IMX_SC_R_MIPI_0_I2C_1 396U 407 #define IMX_SC_R_MIPI_1 397U 408 #define IMX_SC_R_MIPI_1_PWM_0 398U 409 #define IMX_SC_R_MIPI_1_I2C_0 399U 410 #define IMX_SC_R_MIPI_1_I2C_1 400U 411 #define IMX_SC_R_CSI_0 401U 412 #define IMX_SC_R_CSI_0_PWM_0 402U 413 #define IMX_SC_R_CSI_0_I2C_0 403U 414 #define IMX_SC_R_CSI_1 404U 415 #define IMX_SC_R_CSI_1_PWM_0 405U 416 #define IMX_SC_R_CSI_1_I2C_0 406U 417 #define IMX_SC_R_HDMI 407U 418 #define IMX_SC_R_HDMI_I2S 408U 419 #define IMX_SC_R_HDMI_I2C_0 409U 420 #define IMX_SC_R_HDMI_PLL_0 410U 421 #define IMX_SC_R_HDMI_RX 411U 422 #define IMX_SC_R_HDMI_RX_BYPASS 412U 423 #define IMX_SC_R_HDMI_RX_I2C_0 413U 424 #define IMX_SC_R_ASRC_0 414U 425 #define IMX_SC_R_ESAI_0 415U 426 #define IMX_SC_R_SPDIF_0 416U 427 #define IMX_SC_R_SPDIF_1 417U 428 #define IMX_SC_R_SAI_3 418U 429 #define IMX_SC_R_SAI_4 419U 430 #define IMX_SC_R_SAI_5 420U 431 #define IMX_SC_R_GPT_5 421U 432 #define IMX_SC_R_GPT_6 422U 433 #define IMX_SC_R_GPT_7 423U 434 #define IMX_SC_R_GPT_8 424U 435 #define IMX_SC_R_GPT_9 425U 436 #define IMX_SC_R_GPT_10 426U 437 #define IMX_SC_R_DMA_2_CH5 427U 438 #define IMX_SC_R_DMA_2_CH6 428U 439 #define IMX_SC_R_DMA_2_CH7 429U 440 #define IMX_SC_R_DMA_2_CH8 430U 441 #define IMX_SC_R_DMA_2_CH9 431U 442 #define IMX_SC_R_DMA_2_CH10 432U 443 #define IMX_SC_R_DMA_2_CH11 433U 444 #define IMX_SC_R_DMA_2_CH12 434U 445 #define IMX_SC_R_DMA_2_CH13 435U 446 #define IMX_SC_R_DMA_2_CH14 436U 447 #define IMX_SC_R_DMA_2_CH15 437U 448 #define IMX_SC_R_DMA_2_CH16 438U 449 #define IMX_SC_R_DMA_2_CH17 439U 450 #define IMX_SC_R_DMA_2_CH18 440U 451 #define IMX_SC_R_DMA_2_CH19 441U 452 #define IMX_SC_R_DMA_2_CH20 442U 453 #define IMX_SC_R_DMA_2_CH21 443U 454 #define IMX_SC_R_DMA_2_CH22 444U 455 #define IMX_SC_R_DMA_2_CH23 445U 456 #define IMX_SC_R_DMA_2_CH24 446U 457 #define IMX_SC_R_DMA_2_CH25 447U 458 #define IMX_SC_R_DMA_2_CH26 448U 459 #define IMX_SC_R_DMA_2_CH27 449U 460 #define IMX_SC_R_DMA_2_CH28 450U 461 #define IMX_SC_R_DMA_2_CH29 451U 462 #define IMX_SC_R_DMA_2_CH30 452U 463 #define IMX_SC_R_DMA_2_CH31 453U 464 #define IMX_SC_R_ASRC_1 454U 465 #define IMX_SC_R_ESAI_1 455U 466 #define IMX_SC_R_SAI_6 456U 467 #define IMX_SC_R_SAI_7 457U 468 #define IMX_SC_R_AMIX 458U 469 #define IMX_SC_R_MQS_0 459U 470 #define IMX_SC_R_DMA_3_CH0 460U 471 #define IMX_SC_R_DMA_3_CH1 461U 472 #define IMX_SC_R_DMA_3_CH2 462U 473 #define IMX_SC_R_DMA_3_CH3 463U 474 #define IMX_SC_R_DMA_3_CH4 464U 475 #define IMX_SC_R_DMA_3_CH5 465U 476 #define IMX_SC_R_DMA_3_CH6 466U 477 #define IMX_SC_R_DMA_3_CH7 467U 478 #define IMX_SC_R_DMA_3_CH8 468U 479 #define IMX_SC_R_DMA_3_CH9 469U 480 #define IMX_SC_R_DMA_3_CH10 470U 481 #define IMX_SC_R_DMA_3_CH11 471U 482 #define IMX_SC_R_DMA_3_CH12 472U 483 #define IMX_SC_R_DMA_3_CH13 473U 484 #define IMX_SC_R_DMA_3_CH14 474U 485 #define IMX_SC_R_DMA_3_CH15 475U 486 #define IMX_SC_R_DMA_3_CH16 476U 487 #define IMX_SC_R_DMA_3_CH17 477U 488 #define IMX_SC_R_DMA_3_CH18 478U 489 #define IMX_SC_R_DMA_3_CH19 479U 490 #define IMX_SC_R_DMA_3_CH20 480U 491 #define IMX_SC_R_DMA_3_CH21 481U 492 #define IMX_SC_R_DMA_3_CH22 482U 493 #define IMX_SC_R_DMA_3_CH23 483U 494 #define IMX_SC_R_DMA_3_CH24 484U 495 #define IMX_SC_R_DMA_3_CH25 485U 496 #define IMX_SC_R_DMA_3_CH26 486U 497 #define IMX_SC_R_DMA_3_CH27 487U 498 #define IMX_SC_R_DMA_3_CH28 488U 499 #define IMX_SC_R_DMA_3_CH29 489U 500 #define IMX_SC_R_DMA_3_CH30 490U 501 #define IMX_SC_R_DMA_3_CH31 491U 502 #define IMX_SC_R_AUDIO_PLL_1 492U 503 #define IMX_SC_R_AUDIO_CLK_0 493U 504 #define IMX_SC_R_AUDIO_CLK_1 494U 505 #define IMX_SC_R_MCLK_OUT_0 495U 506 #define IMX_SC_R_MCLK_OUT_1 496U 507 #define IMX_SC_R_PMIC_0 497U 508 #define IMX_SC_R_PMIC_1 498U 509 #define IMX_SC_R_SECO 499U 510 #define IMX_SC_R_CAAM_JR1 500U 511 #define IMX_SC_R_CAAM_JR2 501U 512 #define IMX_SC_R_CAAM_JR3 502U 513 #define IMX_SC_R_SECO_MU_2 503U 514 #define IMX_SC_R_SECO_MU_3 504U 515 #define IMX_SC_R_SECO_MU_4 505U 516 #define IMX_SC_R_HDMI_RX_PWM_0 506U 517 #define IMX_SC_R_A35 507U 518 #define IMX_SC_R_A35_0 508U 519 #define IMX_SC_R_A35_1 509U 520 #define IMX_SC_R_A35_2 510U 521 #define IMX_SC_R_A35_3 511U 522 #define IMX_SC_R_DSP 512U 523 #define IMX_SC_R_DSP_RAM 513U 524 #define IMX_SC_R_CAAM_JR1_OUT 514U 525 #define IMX_SC_R_CAAM_JR2_OUT 515U 526 #define IMX_SC_R_CAAM_JR3_OUT 516U 527 #define IMX_SC_R_VPU_DEC_0 517U 528 #define IMX_SC_R_VPU_ENC_0 518U 529 #define IMX_SC_R_CAAM_JR0 519U 530 #define IMX_SC_R_CAAM_JR0_OUT 520U 531 #define IMX_SC_R_PMIC_2 521U 532 #define IMX_SC_R_DBLOGIC 522U 533 #define IMX_SC_R_HDMI_PLL_1 523U 534 #define IMX_SC_R_BOARD_R0 524U 535 #define IMX_SC_R_BOARD_R1 525U 536 #define IMX_SC_R_BOARD_R2 526U 537 #define IMX_SC_R_BOARD_R3 527U 538 #define IMX_SC_R_BOARD_R4 528U 539 #define IMX_SC_R_BOARD_R5 529U 540 #define IMX_SC_R_BOARD_R6 530U 541 #define IMX_SC_R_BOARD_R7 531U 542 #define IMX_SC_R_MJPEG_DEC_MP 532U 543 #define IMX_SC_R_MJPEG_ENC_MP 533U 544 #define IMX_SC_R_VPU_TS_0 534U 545 #define IMX_SC_R_VPU_MU_0 535U 546 #define IMX_SC_R_VPU_MU_1 536U 547 #define IMX_SC_R_VPU_MU_2 537U 548 #define IMX_SC_R_VPU_MU_3 538U 549 #define IMX_SC_R_VPU_ENC_1 539U 550 #define IMX_SC_R_VPU 540U 551 #define IMX_SC_R_DMA_5_CH0 541U 552 #define IMX_SC_R_DMA_5_CH1 542U 553 #define IMX_SC_R_DMA_5_CH2 543U 554 #define IMX_SC_R_DMA_5_CH3 544U 555 #define IMX_SC_R_ATTESTATION 545U 556 #define IMX_SC_R_LAST 546U 557 558 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ */ 559
