1 /* 2 * Copyright (c) 2025 Silicon Laboratories Inc. 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Pin Control for Silicon Labs XG29 devices 6 * 7 * This file was generated by the script gen_pinctrl.py in the hal_silabs module. 8 * Do not manually edit. 9 */ 10 11 #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ 12 #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ 13 14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h> 15 16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) 17 18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2) 19 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3) 20 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4) 21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1) 22 23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1) 24 #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3) 25 #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4) 26 #define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5) 27 #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6) 28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2) 29 30 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1) 31 #define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 3) 32 #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 4) 33 #define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 3, 5) 34 #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 27, 1, 4, 6) 35 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 27, 0, 0, 2) 36 37 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 35, 1, 0, 1) 38 #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 35, 1, 1, 2) 39 #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 35, 1, 2, 3) 40 41 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1) 42 #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2) 43 44 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1) 45 #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2) 46 47 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 48, 1, 0, 1) 48 #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 48, 1, 1, 2) 49 50 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 52, 1, 0, 1) 51 #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 52, 1, 1, 2) 52 #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 52, 1, 2, 3) 53 #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 52, 1, 3, 4) 54 #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 52, 1, 4, 5) 55 #define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 52, 1, 5, 6) 56 #define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 52, 1, 6, 7) 57 #define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 52, 1, 7, 8) 58 #define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 52, 1, 8, 9) 59 #define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 52, 1, 9, 10) 60 #define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 52, 1, 10, 11) 61 #define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 52, 1, 11, 12) 62 #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 52, 1, 12, 13) 63 #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 52, 1, 13, 14) 64 #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 52, 1, 14, 16) 65 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 52, 0, 0, 15) 66 67 #define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1) 68 #define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 2) 69 #define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 3) 70 71 #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1) 72 #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2) 73 #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3) 74 #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4) 75 #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5) 76 #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6) 77 #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 75, 1, 6, 7) 78 #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 75, 1, 7, 8) 79 #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 75, 1, 8, 9) 80 #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 75, 1, 9, 10) 81 #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 75, 1, 10, 11) 82 #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 75, 1, 11, 12) 83 #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 12, 13) 84 #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 13, 14) 85 #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 14, 15) 86 #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 15, 16) 87 88 #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1) 89 #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2) 90 #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3) 91 #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4) 92 #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5) 93 #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6) 94 95 #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1) 96 #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2) 97 #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3) 98 #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4) 99 #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5) 100 #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6) 101 102 #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1) 103 #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2) 104 #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3) 105 #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4) 106 #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5) 107 #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6) 108 109 #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1) 110 #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2) 111 #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3) 112 #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4) 113 #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5) 114 #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6) 115 116 #define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1) 117 #define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 2) 118 #define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 3) 119 #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 4) 120 #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 5) 121 #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 125, 1, 5, 6) 122 123 #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1) 124 #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3) 125 #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4) 126 #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5) 127 #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6) 128 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2) 129 130 #define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 141, 1, 0, 1) 131 #define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 141, 1, 1, 3) 132 #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 141, 1, 2, 4) 133 #define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 141, 1, 3, 5) 134 #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 141, 1, 4, 6) 135 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 141, 0, 0, 2) 136 137 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) 138 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) 139 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) 140 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) 141 #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) 142 #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) 143 #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) 144 #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) 145 #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) 146 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) 147 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) 148 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) 149 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) 150 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) 151 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) 152 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) 153 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) 154 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) 155 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) 156 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) 157 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) 158 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) 159 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) 160 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) 161 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) 162 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) 163 164 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) 165 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) 166 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) 167 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) 168 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) 169 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) 170 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) 171 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) 172 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) 173 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) 174 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) 175 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) 176 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) 177 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) 178 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) 179 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) 180 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) 181 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) 182 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) 183 #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) 184 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) 185 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) 186 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) 187 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) 188 #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) 189 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) 190 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) 191 #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) 192 #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) 193 #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) 194 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) 195 #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) 196 #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) 197 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) 198 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) 199 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) 200 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) 201 #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) 202 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) 203 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) 204 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) 205 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) 206 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) 207 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) 208 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) 209 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) 210 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) 211 #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) 212 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) 213 #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) 214 215 #define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) 216 #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) 217 #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) 218 #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) 219 #define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) 220 #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) 221 #define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) 222 #define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) 223 #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) 224 #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) 225 #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) 226 #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) 227 #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) 228 #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) 229 #define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0) 230 #define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1) 231 #define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2) 232 #define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3) 233 #define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4) 234 #define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5) 235 #define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6) 236 #define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7) 237 #define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0) 238 #define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1) 239 #define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2) 240 #define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3) 241 #define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) 242 #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) 243 #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) 244 #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) 245 #define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) 246 #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) 247 #define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) 248 #define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) 249 #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) 250 #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) 251 #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) 252 #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) 253 #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) 254 #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) 255 #define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0) 256 #define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1) 257 #define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2) 258 #define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3) 259 #define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4) 260 #define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5) 261 #define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6) 262 #define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7) 263 #define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0) 264 #define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1) 265 #define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2) 266 #define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3) 267 #define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) 268 #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) 269 #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) 270 #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) 271 #define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) 272 #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) 273 #define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) 274 #define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) 275 #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) 276 #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) 277 #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) 278 #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) 279 #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) 280 #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) 281 #define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0) 282 #define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1) 283 #define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2) 284 #define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3) 285 #define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4) 286 #define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5) 287 #define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6) 288 #define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7) 289 #define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0) 290 #define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1) 291 #define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2) 292 #define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3) 293 #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) 294 #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) 295 #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) 296 #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) 297 #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) 298 #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) 299 #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) 300 #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) 301 #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) 302 #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) 303 #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) 304 #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) 305 #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) 306 #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) 307 #define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0) 308 #define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1) 309 #define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2) 310 #define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3) 311 #define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4) 312 #define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5) 313 #define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6) 314 #define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7) 315 #define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0) 316 #define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1) 317 #define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2) 318 #define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3) 319 #define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) 320 #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) 321 #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) 322 #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) 323 #define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) 324 #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) 325 #define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) 326 #define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) 327 #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) 328 #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) 329 #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) 330 #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) 331 #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) 332 #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) 333 #define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0) 334 #define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1) 335 #define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2) 336 #define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3) 337 #define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4) 338 #define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5) 339 #define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6) 340 #define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7) 341 #define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0) 342 #define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1) 343 #define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2) 344 #define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3) 345 #define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) 346 #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) 347 #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) 348 #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) 349 #define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) 350 #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) 351 #define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) 352 #define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) 353 #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) 354 #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) 355 #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) 356 #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) 357 #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) 358 #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) 359 #define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0) 360 #define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1) 361 #define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2) 362 #define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3) 363 #define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4) 364 #define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5) 365 #define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6) 366 #define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7) 367 #define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0) 368 #define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1) 369 #define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2) 370 #define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3) 371 372 #define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0) 373 #define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1) 374 #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2) 375 #define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3) 376 #define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4) 377 #define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5) 378 #define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6) 379 #define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7) 380 #define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8) 381 #define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0) 382 #define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1) 383 #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2) 384 #define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3) 385 #define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4) 386 #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0) 387 #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1) 388 #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2) 389 #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3) 390 #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4) 391 #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5) 392 #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6) 393 #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7) 394 #define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0) 395 #define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1) 396 #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2) 397 #define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3) 398 #define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0) 399 #define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1) 400 #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2) 401 #define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3) 402 #define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4) 403 #define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5) 404 #define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6) 405 #define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7) 406 #define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8) 407 #define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0) 408 #define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1) 409 #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2) 410 #define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3) 411 #define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4) 412 #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0) 413 #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1) 414 #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2) 415 #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3) 416 #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4) 417 #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5) 418 #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6) 419 #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7) 420 #define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0) 421 #define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1) 422 #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2) 423 #define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3) 424 #define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0) 425 #define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1) 426 #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2) 427 #define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3) 428 #define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4) 429 #define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5) 430 #define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6) 431 #define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7) 432 #define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8) 433 #define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0) 434 #define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1) 435 #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2) 436 #define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3) 437 #define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4) 438 #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0) 439 #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1) 440 #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2) 441 #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3) 442 #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4) 443 #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5) 444 #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6) 445 #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7) 446 #define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0) 447 #define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1) 448 #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2) 449 #define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3) 450 #define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0) 451 #define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1) 452 #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2) 453 #define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3) 454 #define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4) 455 #define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5) 456 #define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6) 457 #define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7) 458 #define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8) 459 #define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0) 460 #define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1) 461 #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2) 462 #define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3) 463 #define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4) 464 #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0) 465 #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1) 466 #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2) 467 #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3) 468 #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4) 469 #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5) 470 #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6) 471 #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7) 472 #define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0) 473 #define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1) 474 #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2) 475 #define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3) 476 #define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0) 477 #define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1) 478 #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2) 479 #define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3) 480 #define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4) 481 #define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5) 482 #define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6) 483 #define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7) 484 #define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8) 485 #define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0) 486 #define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1) 487 #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2) 488 #define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3) 489 #define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4) 490 #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0) 491 #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1) 492 #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2) 493 #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3) 494 #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4) 495 #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5) 496 #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6) 497 #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7) 498 #define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0) 499 #define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1) 500 #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2) 501 #define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3) 502 #define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0) 503 #define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1) 504 #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2) 505 #define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3) 506 #define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4) 507 #define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5) 508 #define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6) 509 #define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7) 510 #define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8) 511 #define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0) 512 #define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1) 513 #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2) 514 #define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3) 515 #define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4) 516 #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0) 517 #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1) 518 #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2) 519 #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3) 520 #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4) 521 #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5) 522 #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6) 523 #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7) 524 #define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0) 525 #define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1) 526 #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2) 527 #define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3) 528 529 #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) 530 #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) 531 #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) 532 #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) 533 #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) 534 #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) 535 #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) 536 #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) 537 #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) 538 #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) 539 #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) 540 #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) 541 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) 542 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) 543 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) 544 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) 545 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) 546 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) 547 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) 548 #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) 549 #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) 550 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) 551 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) 552 #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) 553 #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) 554 #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) 555 #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) 556 #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) 557 #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) 558 #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) 559 #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) 560 #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) 561 #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) 562 #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) 563 #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) 564 #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) 565 566 #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) 567 #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) 568 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) 569 #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) 570 #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) 571 #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) 572 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) 573 #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) 574 #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) 575 #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) 576 #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) 577 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) 578 #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) 579 #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) 580 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) 581 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) 582 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) 583 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) 584 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) 585 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) 586 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) 587 #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) 588 #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) 589 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) 590 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) 591 #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) 592 #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) 593 #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) 594 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) 595 #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) 596 #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) 597 #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) 598 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) 599 #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) 600 #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) 601 #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) 602 #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) 603 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) 604 #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) 605 #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) 606 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) 607 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) 608 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) 609 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) 610 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) 611 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) 612 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) 613 #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) 614 #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) 615 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) 616 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) 617 #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) 618 619 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) 620 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) 621 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) 622 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) 623 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) 624 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) 625 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) 626 #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) 627 #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) 628 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) 629 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) 630 #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) 631 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) 632 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) 633 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) 634 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) 635 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) 636 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) 637 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) 638 #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) 639 #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) 640 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) 641 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) 642 #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) 643 644 #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) 645 #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) 646 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) 647 #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) 648 #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) 649 #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) 650 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) 651 #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) 652 #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) 653 #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) 654 #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) 655 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) 656 #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) 657 #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) 658 #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) 659 #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) 660 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) 661 #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) 662 #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) 663 #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) 664 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) 665 #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) 666 #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) 667 #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) 668 #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) 669 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) 670 #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) 671 #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) 672 673 #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) 674 #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) 675 #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) 676 #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) 677 #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) 678 #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) 679 #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) 680 #define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) 681 #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) 682 #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) 683 #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) 684 #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) 685 #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) 686 #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) 687 #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) 688 #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) 689 #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) 690 #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) 691 #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) 692 #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) 693 #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) 694 #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) 695 #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) 696 #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) 697 #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) 698 #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) 699 #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) 700 #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) 701 #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) 702 #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) 703 #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) 704 #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) 705 #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) 706 #define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) 707 #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) 708 #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) 709 #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) 710 #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) 711 #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) 712 #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) 713 #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) 714 #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) 715 #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) 716 #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) 717 #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) 718 #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) 719 #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) 720 #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) 721 #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) 722 #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) 723 #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) 724 #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) 725 #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) 726 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) 727 #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) 728 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) 729 #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) 730 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) 731 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) 732 #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) 733 #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) 734 #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) 735 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) 736 #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) 737 #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) 738 #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) 739 #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) 740 #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) 741 #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) 742 #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) 743 #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) 744 #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) 745 #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) 746 #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) 747 #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) 748 #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) 749 #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) 750 #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) 751 #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) 752 #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) 753 #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) 754 #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) 755 #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) 756 #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) 757 #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) 758 #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) 759 #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) 760 #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) 761 #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) 762 #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) 763 #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) 764 #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) 765 #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) 766 #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) 767 #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) 768 #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) 769 #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) 770 #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) 771 #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) 772 #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) 773 #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) 774 #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) 775 #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) 776 #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) 777 #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) 778 #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) 779 #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) 780 #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) 781 #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) 782 #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) 783 #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) 784 #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) 785 #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) 786 #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) 787 #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) 788 #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) 789 #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) 790 #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) 791 #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) 792 #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) 793 #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) 794 #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) 795 #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) 796 #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) 797 #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) 798 #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) 799 #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) 800 #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) 801 #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) 802 #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) 803 #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) 804 #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) 805 #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) 806 #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) 807 #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) 808 #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) 809 #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) 810 #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) 811 #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) 812 #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) 813 #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) 814 #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) 815 #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) 816 #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) 817 #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) 818 #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) 819 #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) 820 #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) 821 #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) 822 #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) 823 #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) 824 #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) 825 #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) 826 #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) 827 #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) 828 #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) 829 #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) 830 #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) 831 #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) 832 #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) 833 #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) 834 #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) 835 #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) 836 #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) 837 #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) 838 #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) 839 #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) 840 #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) 841 #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) 842 #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) 843 #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) 844 #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) 845 #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) 846 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) 847 #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) 848 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) 849 #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) 850 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) 851 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) 852 #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) 853 #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) 854 #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) 855 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) 856 #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) 857 #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) 858 #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) 859 #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) 860 #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) 861 #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) 862 #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) 863 #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) 864 #define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) 865 #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) 866 #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) 867 #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) 868 #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) 869 #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) 870 #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) 871 #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) 872 #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) 873 #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) 874 #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) 875 #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) 876 #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) 877 #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) 878 #define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) 879 #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) 880 #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) 881 #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) 882 #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) 883 #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) 884 #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) 885 #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) 886 #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) 887 #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) 888 #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) 889 #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) 890 #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) 891 #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) 892 #define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) 893 #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) 894 #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) 895 #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) 896 #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) 897 #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) 898 #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) 899 900 #define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0) 901 #define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1) 902 #define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2) 903 #define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3) 904 #define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4) 905 #define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5) 906 #define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6) 907 #define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7) 908 #define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8) 909 #define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0) 910 #define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1) 911 #define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2) 912 #define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3) 913 #define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4) 914 #define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0) 915 #define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1) 916 #define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2) 917 #define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3) 918 #define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4) 919 #define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5) 920 #define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6) 921 #define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7) 922 #define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0) 923 #define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1) 924 #define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2) 925 #define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3) 926 #define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0) 927 #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1) 928 #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2) 929 #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3) 930 #define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4) 931 #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5) 932 #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6) 933 #define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7) 934 #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8) 935 #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0) 936 #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1) 937 #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2) 938 #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3) 939 #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4) 940 #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0) 941 #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1) 942 #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2) 943 #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3) 944 #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4) 945 #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5) 946 #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6) 947 #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7) 948 #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0) 949 #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1) 950 #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2) 951 #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3) 952 #define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0) 953 #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1) 954 #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2) 955 #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3) 956 #define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4) 957 #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5) 958 #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6) 959 #define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7) 960 #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8) 961 #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0) 962 #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1) 963 #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2) 964 #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3) 965 #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4) 966 #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0) 967 #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1) 968 #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2) 969 #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3) 970 #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4) 971 #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5) 972 #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6) 973 #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7) 974 #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0) 975 #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1) 976 #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2) 977 #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3) 978 979 #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) 980 #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) 981 #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) 982 #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) 983 #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) 984 #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) 985 #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) 986 #define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) 987 #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) 988 #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) 989 #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) 990 #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) 991 #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) 992 #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) 993 #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) 994 #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) 995 #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) 996 #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) 997 #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) 998 #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) 999 #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) 1000 #define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) 1001 #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) 1002 #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) 1003 #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) 1004 #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) 1005 #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) 1006 #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) 1007 #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) 1008 #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) 1009 #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) 1010 #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) 1011 #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) 1012 #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) 1013 #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) 1014 #define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) 1015 #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) 1016 #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) 1017 #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) 1018 #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) 1019 #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) 1020 #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) 1021 #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) 1022 #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) 1023 #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) 1024 #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) 1025 #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) 1026 #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) 1027 #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) 1028 #define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) 1029 #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) 1030 #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) 1031 #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) 1032 #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) 1033 #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) 1034 #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) 1035 #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) 1036 #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) 1037 #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) 1038 #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) 1039 #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) 1040 #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) 1041 #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) 1042 #define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) 1043 #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) 1044 #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) 1045 #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) 1046 #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) 1047 #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) 1048 #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) 1049 #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) 1050 #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) 1051 #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) 1052 #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) 1053 #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) 1054 #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) 1055 #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) 1056 #define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) 1057 #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) 1058 #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) 1059 #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) 1060 #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) 1061 #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) 1062 #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) 1063 #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) 1064 #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) 1065 #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) 1066 #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) 1067 #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) 1068 #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) 1069 #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) 1070 #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) 1071 #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) 1072 #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) 1073 #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) 1074 #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) 1075 #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) 1076 #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) 1077 #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) 1078 #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) 1079 #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) 1080 #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) 1081 #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) 1082 #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) 1083 #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) 1084 #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) 1085 #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) 1086 #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) 1087 #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) 1088 #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) 1089 #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) 1090 #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) 1091 #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) 1092 #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) 1093 #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) 1094 #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) 1095 #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) 1096 #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) 1097 #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) 1098 #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) 1099 #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) 1100 #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) 1101 #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) 1102 #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) 1103 #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) 1104 #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) 1105 #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) 1106 #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) 1107 #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) 1108 #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) 1109 #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) 1110 #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) 1111 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) 1112 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) 1113 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) 1114 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) 1115 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) 1116 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) 1117 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) 1118 #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) 1119 #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) 1120 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) 1121 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) 1122 #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) 1123 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) 1124 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) 1125 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) 1126 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) 1127 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) 1128 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) 1129 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) 1130 #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) 1131 #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) 1132 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) 1133 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) 1134 #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) 1135 #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) 1136 #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) 1137 #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) 1138 #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) 1139 #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) 1140 #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) 1141 #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) 1142 #define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) 1143 #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) 1144 #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) 1145 #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) 1146 #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) 1147 #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) 1148 #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) 1149 #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) 1150 #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) 1151 #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) 1152 #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) 1153 #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) 1154 #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) 1155 #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) 1156 #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) 1157 #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) 1158 #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) 1159 #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) 1160 #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) 1161 #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) 1162 #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) 1163 #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) 1164 #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) 1165 #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) 1166 #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) 1167 #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) 1168 #define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) 1169 #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) 1170 #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) 1171 #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) 1172 #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) 1173 #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) 1174 #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) 1175 #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) 1176 #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) 1177 #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) 1178 #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) 1179 #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) 1180 #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) 1181 #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) 1182 #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) 1183 #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) 1184 #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) 1185 #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) 1186 #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) 1187 #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) 1188 #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) 1189 #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) 1190 #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) 1191 #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) 1192 #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) 1193 #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) 1194 #define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) 1195 #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) 1196 #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) 1197 #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) 1198 #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) 1199 #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) 1200 #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) 1201 #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) 1202 #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) 1203 #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) 1204 #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) 1205 #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) 1206 #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) 1207 #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) 1208 #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) 1209 #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) 1210 #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) 1211 #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) 1212 #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) 1213 #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) 1214 #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) 1215 #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) 1216 #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) 1217 #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) 1218 #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) 1219 #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) 1220 #define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) 1221 #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) 1222 #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) 1223 #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) 1224 #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) 1225 #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) 1226 #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) 1227 #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) 1228 #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) 1229 #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) 1230 #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) 1231 #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) 1232 #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) 1233 #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) 1234 #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) 1235 #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) 1236 #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) 1237 #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) 1238 #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) 1239 1240 #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) 1241 #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) 1242 #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) 1243 #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) 1244 #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) 1245 #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) 1246 #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) 1247 #define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) 1248 #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) 1249 #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) 1250 #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) 1251 #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) 1252 #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) 1253 #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) 1254 #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) 1255 #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) 1256 #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) 1257 #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) 1258 #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) 1259 #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) 1260 #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) 1261 #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) 1262 #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) 1263 #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) 1264 #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) 1265 #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) 1266 #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) 1267 #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) 1268 #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) 1269 #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) 1270 #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) 1271 #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) 1272 #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) 1273 #define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) 1274 #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) 1275 #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) 1276 #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) 1277 #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) 1278 #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) 1279 #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) 1280 #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) 1281 #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) 1282 #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) 1283 #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) 1284 #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) 1285 #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) 1286 #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) 1287 #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) 1288 #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) 1289 #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) 1290 #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) 1291 #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) 1292 #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) 1293 #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) 1294 #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) 1295 #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) 1296 #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) 1297 #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) 1298 #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) 1299 #define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) 1300 #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) 1301 #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) 1302 #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) 1303 #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) 1304 #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) 1305 #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) 1306 #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) 1307 #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) 1308 #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) 1309 #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) 1310 #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) 1311 #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) 1312 #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) 1313 #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) 1314 #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) 1315 #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) 1316 #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) 1317 #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) 1318 #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) 1319 #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) 1320 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) 1321 #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) 1322 #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) 1323 #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) 1324 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) 1325 #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) 1326 #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) 1327 #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) 1328 #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) 1329 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) 1330 #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) 1331 #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) 1332 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) 1333 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) 1334 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) 1335 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) 1336 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) 1337 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) 1338 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) 1339 #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) 1340 #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) 1341 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) 1342 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) 1343 #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) 1344 #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) 1345 #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) 1346 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) 1347 #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) 1348 #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) 1349 #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) 1350 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) 1351 #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) 1352 #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) 1353 #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) 1354 #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) 1355 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) 1356 #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) 1357 #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) 1358 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) 1359 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) 1360 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) 1361 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) 1362 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) 1363 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) 1364 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) 1365 #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) 1366 #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) 1367 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) 1368 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) 1369 #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) 1370 #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) 1371 #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) 1372 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) 1373 #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) 1374 #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) 1375 #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) 1376 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) 1377 #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) 1378 #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) 1379 #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) 1380 #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) 1381 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) 1382 #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) 1383 #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) 1384 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) 1385 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) 1386 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) 1387 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) 1388 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) 1389 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) 1390 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) 1391 #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) 1392 #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) 1393 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) 1394 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) 1395 #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) 1396 1397 #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) 1398 #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) 1399 #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) 1400 #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) 1401 #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) 1402 #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) 1403 #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) 1404 #define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) 1405 #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) 1406 #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) 1407 #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) 1408 #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) 1409 #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) 1410 #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) 1411 #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) 1412 #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) 1413 #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) 1414 #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) 1415 #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) 1416 #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) 1417 #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) 1418 #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) 1419 #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) 1420 #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) 1421 #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) 1422 #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) 1423 #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) 1424 #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) 1425 #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) 1426 #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) 1427 #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) 1428 #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) 1429 #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) 1430 #define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) 1431 #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) 1432 #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) 1433 #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) 1434 #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) 1435 #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) 1436 #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) 1437 #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) 1438 #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) 1439 #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) 1440 #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) 1441 #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) 1442 #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) 1443 #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) 1444 #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) 1445 #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) 1446 #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) 1447 #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) 1448 #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) 1449 #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) 1450 #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) 1451 #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) 1452 #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) 1453 #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) 1454 #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) 1455 #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) 1456 #define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) 1457 #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) 1458 #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) 1459 #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) 1460 #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) 1461 #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) 1462 #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) 1463 #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) 1464 #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) 1465 #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) 1466 #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) 1467 #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) 1468 #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) 1469 #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) 1470 #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) 1471 #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) 1472 #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) 1473 #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) 1474 #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) 1475 #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) 1476 #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) 1477 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) 1478 #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) 1479 #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) 1480 #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) 1481 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) 1482 #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) 1483 #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) 1484 #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) 1485 #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) 1486 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) 1487 #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) 1488 #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) 1489 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) 1490 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) 1491 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) 1492 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) 1493 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) 1494 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) 1495 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) 1496 #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) 1497 #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) 1498 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) 1499 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) 1500 #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) 1501 #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) 1502 #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) 1503 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) 1504 #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) 1505 #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) 1506 #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) 1507 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) 1508 #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) 1509 #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) 1510 #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) 1511 #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) 1512 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) 1513 #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) 1514 #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) 1515 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) 1516 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) 1517 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) 1518 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) 1519 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) 1520 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) 1521 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) 1522 #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) 1523 #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) 1524 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) 1525 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) 1526 #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) 1527 #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) 1528 #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) 1529 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) 1530 #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) 1531 #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) 1532 #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) 1533 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) 1534 #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) 1535 #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) 1536 #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) 1537 #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) 1538 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) 1539 #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) 1540 #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) 1541 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) 1542 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) 1543 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) 1544 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) 1545 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) 1546 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) 1547 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) 1548 #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) 1549 #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) 1550 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) 1551 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) 1552 #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) 1553 1554 #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) 1555 #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) 1556 #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) 1557 #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) 1558 #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) 1559 #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) 1560 #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) 1561 #define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) 1562 #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) 1563 #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) 1564 #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) 1565 #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) 1566 #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) 1567 #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) 1568 #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) 1569 #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) 1570 #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) 1571 #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) 1572 #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) 1573 #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) 1574 #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) 1575 #define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) 1576 #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) 1577 #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) 1578 #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) 1579 #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) 1580 #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) 1581 #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) 1582 #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) 1583 #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) 1584 #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) 1585 #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) 1586 #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) 1587 #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) 1588 #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) 1589 #define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) 1590 #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) 1591 #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) 1592 #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) 1593 #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) 1594 #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) 1595 #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) 1596 #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) 1597 #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) 1598 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) 1599 #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) 1600 #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) 1601 #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) 1602 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) 1603 #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) 1604 #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) 1605 #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) 1606 #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) 1607 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) 1608 #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) 1609 #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) 1610 #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) 1611 #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) 1612 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) 1613 #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) 1614 #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) 1615 #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) 1616 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) 1617 #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) 1618 #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) 1619 #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) 1620 #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) 1621 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) 1622 #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) 1623 #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) 1624 #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) 1625 #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) 1626 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) 1627 #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) 1628 #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) 1629 #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) 1630 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) 1631 #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) 1632 #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) 1633 #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) 1634 #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) 1635 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) 1636 #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) 1637 #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) 1638 1639 #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) 1640 #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) 1641 #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) 1642 #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) 1643 #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) 1644 #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) 1645 #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) 1646 #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) 1647 #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) 1648 #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) 1649 #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) 1650 #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) 1651 #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) 1652 #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) 1653 #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) 1654 #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) 1655 #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) 1656 #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) 1657 #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) 1658 #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) 1659 #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) 1660 #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) 1661 #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) 1662 #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) 1663 #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) 1664 #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) 1665 #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) 1666 #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) 1667 #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) 1668 #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) 1669 #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) 1670 #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) 1671 #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) 1672 #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) 1673 #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) 1674 #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) 1675 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) 1676 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) 1677 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) 1678 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) 1679 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) 1680 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) 1681 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) 1682 #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) 1683 #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) 1684 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) 1685 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) 1686 #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) 1687 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) 1688 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) 1689 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) 1690 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) 1691 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) 1692 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) 1693 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) 1694 #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) 1695 #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) 1696 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) 1697 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) 1698 #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) 1699 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) 1700 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) 1701 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) 1702 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) 1703 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) 1704 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) 1705 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) 1706 #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) 1707 #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) 1708 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) 1709 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) 1710 #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) 1711 1712 #define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) 1713 #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) 1714 #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) 1715 #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) 1716 #define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) 1717 #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) 1718 #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) 1719 #define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) 1720 #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) 1721 #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) 1722 #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) 1723 #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) 1724 #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) 1725 #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) 1726 #define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) 1727 #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) 1728 #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) 1729 #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) 1730 #define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) 1731 #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) 1732 #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) 1733 #define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) 1734 #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) 1735 #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) 1736 #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) 1737 #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) 1738 #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) 1739 #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) 1740 #define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) 1741 #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) 1742 #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) 1743 #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) 1744 #define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) 1745 #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) 1746 #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) 1747 #define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) 1748 #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) 1749 #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) 1750 #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) 1751 #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) 1752 #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) 1753 #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) 1754 #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) 1755 #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) 1756 #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) 1757 #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) 1758 #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) 1759 #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) 1760 #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) 1761 #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) 1762 #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) 1763 #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) 1764 #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) 1765 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) 1766 #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) 1767 #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) 1768 #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) 1769 #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) 1770 #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) 1771 #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) 1772 #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) 1773 #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) 1774 #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) 1775 #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) 1776 #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) 1777 #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) 1778 #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) 1779 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) 1780 #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) 1781 #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) 1782 #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) 1783 #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) 1784 #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) 1785 #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) 1786 #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) 1787 #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) 1788 #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) 1789 #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) 1790 #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) 1791 #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) 1792 #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) 1793 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) 1794 #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) 1795 #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) 1796 1797 #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) 1798 #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) 1799 #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) 1800 #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) 1801 #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) 1802 #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) 1803 #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) 1804 #define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) 1805 #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) 1806 #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) 1807 #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) 1808 #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) 1809 #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) 1810 #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) 1811 #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) 1812 #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) 1813 #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) 1814 #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) 1815 #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) 1816 #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) 1817 #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) 1818 #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) 1819 #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) 1820 #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) 1821 #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) 1822 #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) 1823 #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) 1824 #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) 1825 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) 1826 #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) 1827 #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) 1828 #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) 1829 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) 1830 #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) 1831 #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) 1832 #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) 1833 #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) 1834 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) 1835 #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) 1836 #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) 1837 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) 1838 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) 1839 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) 1840 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) 1841 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) 1842 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) 1843 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) 1844 #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) 1845 #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) 1846 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) 1847 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) 1848 #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) 1849 #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) 1850 #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) 1851 #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) 1852 #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) 1853 #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) 1854 #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) 1855 #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) 1856 #define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) 1857 #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) 1858 #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) 1859 #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) 1860 #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) 1861 #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) 1862 #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) 1863 #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) 1864 #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) 1865 #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) 1866 #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) 1867 #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) 1868 #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) 1869 #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) 1870 #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) 1871 #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) 1872 #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) 1873 #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) 1874 #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) 1875 #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) 1876 #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) 1877 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) 1878 #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) 1879 #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) 1880 #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) 1881 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) 1882 #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) 1883 #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) 1884 #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) 1885 #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) 1886 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) 1887 #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) 1888 #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) 1889 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) 1890 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) 1891 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) 1892 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) 1893 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) 1894 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) 1895 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) 1896 #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) 1897 #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) 1898 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) 1899 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) 1900 #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) 1901 #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) 1902 #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) 1903 #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) 1904 #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) 1905 #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) 1906 #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) 1907 #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) 1908 #define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) 1909 #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) 1910 #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) 1911 #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) 1912 #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) 1913 #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) 1914 #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) 1915 #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) 1916 #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) 1917 #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) 1918 #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) 1919 #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) 1920 #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) 1921 #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) 1922 #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) 1923 #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) 1924 #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) 1925 #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) 1926 #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) 1927 #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) 1928 #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) 1929 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) 1930 #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) 1931 #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) 1932 #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) 1933 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) 1934 #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) 1935 #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) 1936 #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) 1937 #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) 1938 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) 1939 #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) 1940 #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) 1941 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) 1942 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) 1943 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) 1944 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) 1945 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) 1946 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) 1947 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) 1948 #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) 1949 #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) 1950 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) 1951 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) 1952 #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) 1953 1954 #define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) 1955 #define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) 1956 #define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) 1957 #define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) 1958 #define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) 1959 #define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) 1960 #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) 1961 #define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7) 1962 #define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8) 1963 #define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) 1964 #define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) 1965 #define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2) 1966 #define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3) 1967 #define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4) 1968 #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) 1969 #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) 1970 #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) 1971 #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) 1972 #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) 1973 #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) 1974 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) 1975 #define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7) 1976 #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8) 1977 #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) 1978 #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) 1979 #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2) 1980 #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3) 1981 #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4) 1982 #define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) 1983 #define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) 1984 #define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) 1985 #define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) 1986 #define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) 1987 #define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) 1988 #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) 1989 #define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7) 1990 #define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8) 1991 #define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) 1992 #define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) 1993 #define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2) 1994 #define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3) 1995 #define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4) 1996 #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) 1997 #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) 1998 #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) 1999 #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) 2000 #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) 2001 #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) 2002 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) 2003 #define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7) 2004 #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8) 2005 #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) 2006 #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) 2007 #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2) 2008 #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3) 2009 #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4) 2010 #define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) 2011 #define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) 2012 #define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) 2013 #define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) 2014 #define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) 2015 #define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) 2016 #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) 2017 #define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7) 2018 #define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8) 2019 #define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) 2020 #define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) 2021 #define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2) 2022 #define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3) 2023 #define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4) 2024 #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) 2025 #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) 2026 #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) 2027 #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) 2028 #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) 2029 #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) 2030 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) 2031 #define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7) 2032 #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8) 2033 #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) 2034 #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) 2035 #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2) 2036 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3) 2037 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4) 2038 2039 #define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1) 2040 #define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2) 2041 #define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1) 2042 #define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2) 2043 #define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1) 2044 #define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2) 2045 #define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1) 2046 #define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2) 2047 #define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1) 2048 #define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2) 2049 #define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1) 2050 #define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2) 2051 #define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1) 2052 #define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2) 2053 #define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1) 2054 #define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2) 2055 #define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1) 2056 #define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2) 2057 #define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1) 2058 #define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2) 2059 #define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1) 2060 #define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2) 2061 #define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1) 2062 #define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2) 2063 2064 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ */ 2065
