1 /* 2 * Copyright (c) 2024 Michael Hope 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __CH32V003_PINCTRL_H__ 8 #define __CH32V003_PINCTRL_H__ 9 10 #define CH32V003_PINMUX_PORT_PA 0 11 #define CH32V003_PINMUX_PORT_PC 1 12 #define CH32V003_PINMUX_PORT_PD 2 13 14 /* 15 * Defines the starting bit for the remap field. Note that the I2C1 and USART1 fields are not 16 * contigious. 17 */ 18 #define CH32V003_PINMUX_SPI1_RM 0 19 #define CH32V003_PINMUX_I2C1_RM 1 20 #define CH32V003_PINMUX_I2C1_RM1 22 21 #define CH32V003_PINMUX_USART1_RM 2 22 #define CH32V003_PINMUX_USART1_RM1 21 23 #define CH32V003_PINMUX_TIM1_RM 6 24 #define CH32V003_PINMUX_TIM1_RM1 23 25 #define CH32V003_PINMUX_TIM2_RM 8 26 27 /* Port number with 0-2 */ 28 #define CH32V003_PINCTRL_PORT_SHIFT 0 29 /* Pin number 0-15 */ 30 #define CH32V003_PINCTRL_PIN_SHIFT 2 31 /* Base remap bit 0-31 */ 32 #define CH32V003_PINCTRL_RM_BASE_SHIFT 6 33 /* Function remapping ID 0-3 */ 34 #define CH32V003_PINCTRL_RM_SHIFT 11 35 36 #define CH32V003_PINMUX_DEFINE(port, pin, rm, remapping) \ 37 ((CH32V003_PINMUX_PORT_##port << CH32V003_PINCTRL_PORT_SHIFT) | \ 38 (pin << CH32V003_PINCTRL_PIN_SHIFT) | \ 39 (CH32V003_PINMUX_##rm##_RM << CH32V003_PINCTRL_RM_BASE_SHIFT) | \ 40 (remapping << CH32V003_PINCTRL_RM_SHIFT)) 41 42 #define TIM1_ETR_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 0) 43 #define TIM1_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 1) 44 #define TIM1_ETR_PD4_2 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 2) 45 #define TIM1_ETR_PC2_3 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3) 46 #define TIM1_CH1_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 0) 47 #define TIM1_CH1_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 1) 48 #define TIM1_CH1_PD2_2 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 2) 49 #define TIM1_CH1_PC4_3 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 3) 50 #define TIM1_CH2_PA1_0 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 0) 51 #define TIM1_CH2_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 1) 52 #define TIM1_CH2_PA1_2 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 2) 53 #define TIM1_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 3) 54 #define TIM1_CH3_PC3_0 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 0) 55 #define TIM1_CH3_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, TIM1, 1) 56 #define TIM1_CH3_PC3_2 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 2) 57 #define TIM1_CH3_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 3) 58 #define TIM1_CH4_PC4_0 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 0) 59 #define TIM1_CH4_PD3_1 CH32V003_PINMUX_DEFINE(PD, 3, TIM1, 1) 60 #define TIM1_CH4_PC4_2 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 2) 61 #define TIM1_CH4_PD4_3 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 3) 62 #define TIM1_BKIN_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 0) 63 #define TIM1_BKIN_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 1) 64 #define TIM1_BKIN_PC2_2 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 2) 65 #define TIM1_BKIN_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 3) 66 #define TIM1_CH1N_PD0_0 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 0) 67 #define TIM1_CH1N_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 1) 68 #define TIM1_CH1N_PD0_2 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 2) 69 #define TIM1_CH1N_PC3_3 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 3) 70 #define TIM1_CH2N_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 0) 71 #define TIM1_CH2N_PC4_1 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 1) 72 #define TIM1_CH2N_PA2_2 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 2) 73 #define TIM1_CH2N_PD2_3 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 3) 74 #define TIM1_CH3N_PD1_0 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 0) 75 #define TIM1_CH3N_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 1) 76 #define TIM1_CH3N_PD1_2 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 2) 77 #define TIM1_CH3N_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 3) 78 79 #define TIM2_ETR_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0) 80 #define TIM2_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1) 81 #define TIM2_ETR_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2) 82 #define TIM2_ETR_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3) 83 #define TIM2_CH1_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0) 84 #define TIM2_CH1_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1) 85 #define TIM2_CH1_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2) 86 #define TIM2_CH1_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3) 87 #define TIM2_CH2_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 0) 88 #define TIM2_CH2_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, TIM2, 1) 89 #define TIM2_CH2_PD3_2 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 2) 90 #define TIM2_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM2, 3) 91 #define TIM2_CH3_PC0_0 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 0) 92 #define TIM2_CH3_PD2_1 CH32V003_PINMUX_DEFINE(PD, 2, TIM2, 1) 93 #define TIM2_CH3_PC0_2 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 2) 94 #define TIM2_CH3_PD6_3 CH32V003_PINMUX_DEFINE(PD, 6, TIM2, 3) 95 #define TIM2_CH4_PD7_0 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 0) 96 #define TIM2_CH4_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 1) 97 #define TIM2_CH4_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 2) 98 #define TIM2_CH4_PD5_3 CH32V003_PINMUX_DEFINE(PD, 5, TIM2, 3) 99 100 #define USART1_CK_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, USART1, 0) 101 #define USART1_CK_PD7_1 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 1) 102 #define USART1_CK_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 2) 103 #define USART1_CK_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, USART1, 3) 104 #define USART1_TX_PD5_0 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 0) 105 #define USART1_TX_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, USART1, 1) 106 #define USART1_TX_PD6_2 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 2) 107 #define USART1_TX_PC0_3 CH32V003_PINMUX_DEFINE(PC, 0, USART1, 3) 108 #define USART1_RX_PD6_0 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 0) 109 #define USART1_RX_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, USART1, 1) 110 #define USART1_RX_PD5_2 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 2) 111 #define USART1_RX_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, USART1, 3) 112 #define USART1_CTS_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, USART1, 0) 113 #define USART1_CTS_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, USART1, 1) 114 #define USART1_CTS_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 2) 115 #define USART1_CTS_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 3) 116 #define USART1_RTS_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 0) 117 #define USART1_RTS_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 1) 118 #define USART1_RTS_PC7_2 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 2) 119 #define USART1_RTS_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 3) 120 121 #define SPI1_NSS_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, SPI1, 0) 122 #define SPI1_NSS_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, SPI1, 1) 123 #define SPI1_SCK_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 0) 124 #define SPI1_SCK_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 1) 125 #define SPI1_MISO_PC7_0 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 0) 126 #define SPI1_MISO_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 1) 127 #define SPI1_MOSI_PC6_0 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 0) 128 #define SPI1_MOSI_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 1) 129 130 #define I2C1_SCL_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, I2C1, 0) 131 #define I2C1_SCL_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, I2C1, 1) 132 #define I2C1_SCL_PC5_2 CH32V003_PINMUX_DEFINE(PC, 5, I2C1, 2) 133 #define I2C1_SDA_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, I2C1, 0) 134 #define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1) 135 #define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2) 136 137 #endif /* __CH32V003_PINCTRL_H__ */ 138
