1 /* 2 * Copyright (c) 2022 ITE Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_ 8 9 10 #define IT8XXX2_ECPM_CGCTRL4R_OFF 0x09 11 /* 12 * The clock gate offsets combine the register offset from ECPM_BASE and the 13 * mask within that register into one value. These are used for 14 * clock_enable_peripheral() and clock_disable_peripheral() 15 */ 16 #define CGC_OFFSET_SMBF ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x80) 17 #define CGC_OFFSET_SMBE ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x40) 18 #define CGC_OFFSET_SMBD ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x20) 19 #define CGC_OFFSET_SMBC ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x10) 20 #define CGC_OFFSET_SMBB ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x08) 21 #define CGC_OFFSET_SMBA ((IT8XXX2_ECPM_CGCTRL4R_OFF << 8) | 0x04) 22 23 /* I2C channel switch selection */ 24 #define I2C_CHA_LOCATE 0 25 #define I2C_CHB_LOCATE 1 26 #define I2C_CHC_LOCATE 2 27 #define I2C_CHD_LOCATE 3 28 #define I2C_CHE_LOCATE 4 29 #define I2C_CHF_LOCATE 5 30 31 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_ */ 32
