1 /*
2  * Copyright (c) 2025 Renesas Electronics Corporation
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_
8 
9 /*********************************RZTN*****************************************/
10 
11 /**
12  * @brief RZTN specific GPIO Flags
13  * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
14  * follows:
15  * - Bit 9..8: Driving ability control
16  * - Bit 12: Schmitt trigger control
17  * - Bit 13: Slew rate control
18  * Example:
19  * Driving ability control: Middle
20  * Schmitt trigger control: Enabled
21  * Slew rate control: Slow
22  * gpio-consumer {
23  *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZTN_GPIO_CFG_SET(1, 1, 0))>;
24  * };
25  */
26 
27 /* GPIO DRCTL register */
28 #define RZTN_GPIO_DRCTL_SHIFT        8U
29 #define RZTN_GPIO_SCHMITT_TRIG_SHIFT 4U
30 #define RZTN_GPIO_SLEW_RATE_SHIFT    5U
31 #define RZTN_GPIO_DRCTL_SET(drive_ability, schmitt_trig, slew_rate)                                \
32 	(((drive_ability) | ((schmitt_trig) << RZTN_GPIO_SCHMITT_TRIG_SHIFT) |                     \
33 	  ((slew_rate) << RZTN_GPIO_SLEW_RATE_SHIFT))                                              \
34 	 << RZTN_GPIO_DRCTL_SHIFT)
35 
36 /*******************************************************************************/
37 
38 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_ */
39