1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x048 13 #define STM32_CLOCK_BUS_AHB2 0x04c 14 #define STM32_CLOCK_BUS_AHB3 0x050 15 #define STM32_CLOCK_BUS_APB1 0x058 16 #define STM32_CLOCK_BUS_APB1_2 0x05c 17 #define STM32_CLOCK_BUS_APB2 0x060 18 19 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 20 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 21 22 /** Domain clocks */ 23 /* RM0434, § Clock configuration register (RCC_CCIPRx) */ 24 25 /** System clock */ 26 /* defined in stm32_common_clocks.h */ 27 /** Fixed clocks */ 28 /* Low speed clocks defined in stm32_common_clocks.h */ 29 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) 31 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) 32 #define STM32_SRC_HSE (STM32_SRC_MSI + 1) 33 /** Bus clock */ 34 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) 35 /** PLL clock outputs */ 36 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) 37 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 38 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 39 /* TODO: PLLSAI clocks */ 40 41 #define STM32_CLOCK_REG_MASK 0xFFU 42 #define STM32_CLOCK_REG_SHIFT 0U 43 #define STM32_CLOCK_SHIFT_MASK 0x1FU 44 #define STM32_CLOCK_SHIFT_SHIFT 8U 45 #define STM32_CLOCK_MASK_MASK 0x7U 46 #define STM32_CLOCK_MASK_SHIFT 13U 47 #define STM32_CLOCK_VAL_MASK 0x7U 48 #define STM32_CLOCK_VAL_SHIFT 16U 49 50 /** 51 * @brief STM32 clock configuration bit field. 52 * 53 * - reg (1/2/3) [ 0 : 7 ] 54 * - shift (0..31) [ 8 : 12 ] 55 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 56 * - val (0..7) [ 16 : 18 ] 57 * 58 * @param reg RCC_CCIPRx register offset 59 * @param shift Position within RCC_CCIPRx. 60 * @param mask Mask for the RCC_CCIPRx field. 61 * @param val Clock value (0, 1, ... 7). 62 */ 63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 64 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 65 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 68 69 /** @brief RCC_CCIPR register offset */ 70 #define CCIPR_REG 0x88 71 72 /** @brief RCC_BDCR register offset */ 73 #define BDCR_REG 0x90 74 75 /** @brief RCC_CSR register offset */ 76 #define CSR_REG 0x94 77 78 /** @brief Device domain clocks selection helpers */ 79 /** CCIPR devices */ 80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) 81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) 82 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) 83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) 84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) 85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) 86 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) 87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) 88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) 89 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) 90 /** BDCR devices */ 91 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 92 /** CSR devices */ 93 #define RFWKP_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG) 94 95 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */ 96
