1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x048 13 #define STM32_CLOCK_BUS_AHB2 0x04c 14 #define STM32_CLOCK_BUS_AHB3 0x050 15 #define STM32_CLOCK_BUS_APB1 0x058 16 #define STM32_CLOCK_BUS_APB1_2 0x05c 17 #define STM32_CLOCK_BUS_APB2 0x060 18 19 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 20 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 21 22 /** Domain clocks */ 23 /* RM0351/RM0432/RM0438, § Clock configuration register (RCC_CCIPRx) */ 24 25 /** System clock */ 26 /* defined in stm32_common_clocks.h */ 27 /** Fixed clocks */ 28 /* Low speed clocks defined in stm32_common_clocks.h */ 29 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) 31 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) 32 /** Bus clock */ 33 #define STM32_SRC_PCLK (STM32_SRC_MSI + 1) 34 /** PLL clock outputs */ 35 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) 36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 38 /* TODO: PLLSAI clocks */ 39 40 /** @brief RCC_CCIPR register offset */ 41 #define CCIPR_REG 0x88 42 #define CCIPR2_REG 0x9C 43 44 /** @brief RCC_BDCR register offset */ 45 #define BDCR_REG 0x90 46 47 /** @brief RCC_CFGRx register offset */ 48 #define CFGR_REG 0x08 49 50 /** @brief Device domain clocks selection helpers */ 51 /** CCIPR devices */ 52 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) 53 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) 54 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) 55 #define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) 56 #define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) 57 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) 58 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) 59 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) 60 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) 61 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) 62 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) 63 #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) 64 #define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG) 65 #define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) 66 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) 67 #define SWPMI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 30, CCIPR_REG) 68 #define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR_REG) 69 /** CCIPR2 devices */ 70 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) 71 #define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG) 72 #define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG) 73 /* #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) */ 74 /* #define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) */ 75 #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG) 76 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) 77 #define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) 78 /** BDCR devices */ 79 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) 80 /** CFGR devices */ 81 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG) 82 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) 83 84 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */ 85
