1 /*
2  * Copyright (c) 2022 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
8 
9 #include "stm32_common_clocks.h"
10 
11 /** Bus gatting clocks */
12 #define STM32_CLOCK_BUS_AHB1    0x01c
13 #define STM32_CLOCK_BUS_APB2    0x020
14 #define STM32_CLOCK_BUS_APB1    0x024
15 
16 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
17 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB1
18 
19 /** Domain clocks */
20 /* RM0038.pdf, §6.3.14 Control/status register (RCC_CSR) */
21 
22 /** System clock */
23 /* defined in stm32_common_clocks.h */
24 /** Fixed clocks  */
25 /* Low speed clocks defined in stm32_common_clocks.h */
26 #define STM32_SRC_HSE		(STM32_SRC_LSI + 1)
27 #define STM32_SRC_HSI		(STM32_SRC_HSE + 1)
28 
29 /** @brief RCC_CSR register offset */
30 #define CSR_REG		0x34
31 
32 #define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG)
33 
34 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */
35