1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus gatting clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x01c 13 #define STM32_CLOCK_BUS_APB2 0x020 14 #define STM32_CLOCK_BUS_APB1 0x024 15 16 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 18 19 /** Domain clocks */ 20 /* RM0038.pdf, §6.3.14 Control/status register (RCC_CSR) */ 21 22 /** System clock */ 23 /* defined in stm32_common_clocks.h */ 24 /** Fixed clocks */ 25 /* Low speed clocks defined in stm32_common_clocks.h */ 26 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 27 28 #define STM32_CLOCK_REG_MASK 0xFFU 29 #define STM32_CLOCK_REG_SHIFT 0U 30 #define STM32_CLOCK_SHIFT_MASK 0x1FU 31 #define STM32_CLOCK_SHIFT_SHIFT 8U 32 #define STM32_CLOCK_MASK_MASK 0x7U 33 #define STM32_CLOCK_MASK_SHIFT 13U 34 #define STM32_CLOCK_VAL_MASK 0x7U 35 #define STM32_CLOCK_VAL_SHIFT 16U 36 37 /** 38 * @brief STM32 clock configuration bit field. 39 * 40 * - reg (1/2/3) [ 0 : 7 ] 41 * - shift (0..31) [ 8 : 12 ] 42 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 43 * - val (0..7) [ 16 : 18 ] 44 * 45 * @param reg RCC_CCIPRx register offset 46 * @param shift Position within RCC_CCIPRx. 47 * @param mask Mask for the RCC_CCIPRx field. 48 * @param val Clock value (0, 1, ... 7). 49 */ 50 #define STM32_CLOCK(val, mask, shift, reg) \ 51 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 52 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 53 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 54 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 55 56 /** @brief RCC_CSR register offset */ 57 #define CSR_REG 0x34 58 59 #define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) 60 61 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */ 62
