1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus gatting clocks */ 12 #define STM32_CLOCK_BUS_IOP 0x02c 13 #define STM32_CLOCK_BUS_AHB1 0x030 14 #define STM32_CLOCK_BUS_APB2 0x034 15 #define STM32_CLOCK_BUS_APB1 0x038 16 17 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP 18 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 19 20 /** Domain clocks */ 21 /* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */ 22 23 /** System clock */ 24 /* defined in stm32_common_clocks.h */ 25 26 /** Fixed clocks */ 27 /* Low speed clocks defined in stm32_common_clocks.h */ 28 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 29 #define STM32_SRC_HSI (STM32_SRC_HSE + 1) 30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) 31 /** Bus clock */ 32 #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1) 33 34 /** @brief RCC_CCIPR register offset */ 35 #define CCIPR_REG 0x4C 36 37 /** @brief RCC_CSR register offset */ 38 #define CSR_REG 0x50 39 40 /** @brief Device domain clocks selection helpers */ 41 /** CCIPR devices */ 42 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) 43 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) 44 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) 45 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) 46 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) 47 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) 48 #define HSI48_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, CCIPR_REG) 49 /** CSR devices */ 50 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG) 51 52 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */ 53
