1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ 8 9 /** Bus gatting clocks */ 10 #define STM32_CLOCK_BUS_IOP 0x02c 11 #define STM32_CLOCK_BUS_AHB1 0x030 12 #define STM32_CLOCK_BUS_APB2 0x034 13 #define STM32_CLOCK_BUS_APB1 0x038 14 15 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP 16 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 17 18 /** Domain clocks */ 19 /* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */ 20 21 /** Fixed clocks */ 22 #define STM32_SRC_HSE 0x001 23 #define STM32_SRC_LSE 0x002 24 #define STM32_SRC_LSI 0x003 25 #define STM32_SRC_HSI 0x004 26 #define STM32_SRC_HSI48 0x005 27 /** System clock */ 28 #define STM32_SRC_SYSCLK 0x006 29 /** Bus clock */ 30 #define STM32_SRC_PCLK 0x007 31 32 #define STM32_CLOCK_REG_MASK 0xFFU 33 #define STM32_CLOCK_REG_SHIFT 0U 34 #define STM32_CLOCK_SHIFT_MASK 0x1FU 35 #define STM32_CLOCK_SHIFT_SHIFT 8U 36 #define STM32_CLOCK_MASK_MASK 0x7U 37 #define STM32_CLOCK_MASK_SHIFT 13U 38 #define STM32_CLOCK_VAL_MASK 0x7U 39 #define STM32_CLOCK_VAL_SHIFT 16U 40 41 /** 42 * @brief STM32 clock configuration bit field. 43 * 44 * - reg (1/2/3) [ 0 : 7 ] 45 * - shift (0..31) [ 8 : 12 ] 46 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 47 * - val (0..7) [ 16 : 18 ] 48 * 49 * @param reg RCC_CCIPRx register offset 50 * @param shift Position within RCC_CCIPRx. 51 * @param mask Mask for the RCC_CCIPRx field. 52 * @param val Clock value (0, 1, ... 7). 53 */ 54 #define STM32_CLOCK(val, mask, shift, reg) \ 55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 57 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 59 60 /** @brief RCC_CCIPR register offset */ 61 #define CCIPR_REG 0x4C 62 63 /** @brief RCC_CSR register offset */ 64 #define CSR_REG 0x50 65 66 /** @brief Device domain clocks selection helpers */ 67 /** CCIPR devices */ 68 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) 69 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) 70 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) 71 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) 72 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) 73 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) 74 #define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG) 75 /** CSR devices */ 76 #define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) 77 /** Dummy: Add a specificier when no selection is possible */ 78 #define NO_SEL 0xFF 79 80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */ 81
