1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus clocks */ 12 #define STM32_CLOCK_BUS_IOP 0x034 13 #define STM32_CLOCK_BUS_AHB1 0x038 14 #define STM32_CLOCK_BUS_APB1 0x03c 15 #define STM32_CLOCK_BUS_APB1_2 0x040 16 17 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP 18 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 19 20 /** Domain clocks */ 21 /* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */ 22 23 /** System clock */ 24 /* defined in stm32_common_clocks.h */ 25 /** Fixed clocks */ 26 /* Low speed clocks defined in stm32_common_clocks.h */ 27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 28 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) 29 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) 30 #define STM32_SRC_HSE (STM32_SRC_MSI + 1) 31 /** Peripheral bus clock */ 32 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) 33 /** PLL clock outputs */ 34 #define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) 35 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 36 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 37 38 /** @brief RCC_CCIPR register offset */ 39 #define CCIPR_REG 0x54 40 #define CCIPR2_REG 0x58 41 42 /** @brief RCC_BDCR register offset */ 43 #define BDCR_REG 0x5C 44 45 /** @brief Device domain clocks selection helpers */ 46 /** CCIPR devices */ 47 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) 48 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) 49 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) 50 #define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG) 51 #define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) 52 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) 53 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) 54 #define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) 55 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) 56 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) 57 #define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG) 58 #define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG) 59 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) 60 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) 61 /** CCIPR2 devices */ 62 #define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) 63 #define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG) 64 #define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG) 65 #define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) 66 /** BDCR devices */ 67 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) 68 69 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */ 70
