1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /** Bus clocks */ 14 #define STM32_CLOCK_BUS_AHB1 0x030 15 #define STM32_CLOCK_BUS_AHB2 0x034 16 #define STM32_CLOCK_BUS_AHB3 0x038 17 #define STM32_CLOCK_BUS_APB1 0x040 18 #define STM32_CLOCK_BUS_APB2 0x044 19 #define STM32_CLOCK_BUS_APB3 0x0A8 20 21 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 22 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 23 24 /** Domain clocks */ 25 /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */ 26 27 /** System clock */ 28 /* defined in stm32_common_clocks.h */ 29 /** Fixed clocks */ 30 /* Low speed clocks defined in stm32_common_clocks.h */ 31 /** PLL clock outputs */ 32 #define STM32_SRC_PLL_P (STM32_SRC_LSI + 1) 33 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 34 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 35 /** I2S sources */ 36 #define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1) 37 /* I2S_CKIN not supported yet */ 38 /* #define STM32_SRC_I2S_CKIN TBD */ 39 40 41 #define STM32_CLOCK_REG_MASK 0xFFU 42 #define STM32_CLOCK_REG_SHIFT 0U 43 #define STM32_CLOCK_SHIFT_MASK 0x1FU 44 #define STM32_CLOCK_SHIFT_SHIFT 8U 45 #define STM32_CLOCK_MASK_MASK 0x7U 46 #define STM32_CLOCK_MASK_SHIFT 13U 47 #define STM32_CLOCK_VAL_MASK 0x7U 48 #define STM32_CLOCK_VAL_SHIFT 16U 49 50 /** 51 * @brief STM32 clock configuration bit field. 52 * 53 * - reg (1/2/3) [ 0 : 7 ] 54 * - shift (0..31) [ 8 : 12 ] 55 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 56 * - val (0..7) [ 16 : 18 ] 57 * 58 * @param reg RCC_CFGRx register offset 59 * @param shift Position within RCC_CFGRx. 60 * @param mask Mask for the RCC_CFGRx field. 61 * @param val Clock value (0, 1, ... 7). 62 */ 63 #define STM32_CLOCK(val, mask, shift, reg) \ 64 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 65 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 68 69 /** @brief RCC_CFGR register offset */ 70 #define CFGR_REG 0x08 71 /** @brief RCC_BDCR register offset */ 72 #define BDCR_REG 0x70 73 74 /** @brief Device domain clocks selection helpers */ 75 /** CFGR devices */ 76 #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) 77 /** BDCR devices */ 78 #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) 79 80 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */ 81
