1 /*
2  * Copyright (c) 2023 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
8 
9 #include "stm32f4_clock.h"
10 
11 /** @brief RCC_DCKCFGR register offset */
12 #define DCKCFGR_REG		0x8C
13 
14 /** @brief Device domain clocks selection helpers */
15 /** DCKCFGR devices */
16 #define CKDFSDM2A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG)
17 #define CKDFSDM1A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG)
18 #define SAI1A_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG)
19 #define SAI1B_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG)
20 #define CLK48M_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR_REG)
21 #define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR_REG)
22 #define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR_REG)
23 
24 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */
25