1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus gatting clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x014 13 #define STM32_CLOCK_BUS_APB2 0x018 14 #define STM32_CLOCK_BUS_APB1 0x01c 15 16 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 18 19 /** Domain clocks */ 20 /* RM0316, §9.4.13 Clock configuration register (RCC_CFGR3) */ 21 22 /** System clock */ 23 /* Defined in stm32_common_clocks.h */ 24 25 /** Fixed clocks */ 26 /* Low speed clocks defined in stm32_common_clocks.h */ 27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 28 /* #define STM32_SRC_HSI48 TDB */ 29 /** Bus clock */ 30 #define STM32_SRC_PCLK (STM32_SRC_HSI + 1) 31 /** PLL clock */ 32 #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) 33 34 /** @brief RCC_CFGRx register offset */ 35 #define CFGR_REG 0x04 36 #define CFGR3_REG 0x30 37 38 /** @brief RCC_BDCR register offset */ 39 #define BDCR_REG 0x20 40 41 /** @brief Device domain clocks selection helpers) */ 42 /** CFGR devices */ 43 #define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) 44 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) 45 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) 46 /** CFGR3 devices */ 47 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) 48 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) 49 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 5, CFGR3_REG) 50 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) 51 #define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CFGR3_REG) 52 #define TIM8_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 9, CFGR3_REG) 53 #define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CFGR3_REG) 54 #define TIM16_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CFGR3_REG) 55 #define TIM17_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR3_REG) 56 #define TIM20_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CFGR3_REG) 57 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) 58 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) 59 #define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CFGR3_REG) 60 #define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR3_REG) 61 #define TIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CFGR3_REG) 62 #define TIM3_4_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 25, CFGR3_REG) 63 /** BDCR devices */ 64 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) 65 66 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */ 67
