1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus gatting clocks */ 12 #define STM32_CLOCK_BUS_AHB1 0x014 13 #define STM32_CLOCK_BUS_APB2 0x018 14 #define STM32_CLOCK_BUS_APB1 0x01c 15 16 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 18 19 /** Domain clocks */ 20 /* RM0316, §9.4.13 Clock configuration register (RCC_CFGR3) */ 21 22 /** System clock */ 23 /* Defined in stm32_common_clocks.h */ 24 25 /** Fixed clocks */ 26 /* Low speed clocks defined in stm32_common_clocks.h */ 27 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 28 /* #define STM32_SRC_HSI48 TDB */ 29 /** Bus clock */ 30 #define STM32_SRC_PCLK (STM32_SRC_HSI + 1) 31 /** PLL clock */ 32 #define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) 33 34 #define STM32_CLOCK_REG_MASK 0xFFU 35 #define STM32_CLOCK_REG_SHIFT 0U 36 #define STM32_CLOCK_SHIFT_MASK 0x1FU 37 #define STM32_CLOCK_SHIFT_SHIFT 8U 38 #define STM32_CLOCK_MASK_MASK 0x7U 39 #define STM32_CLOCK_MASK_SHIFT 13U 40 #define STM32_CLOCK_VAL_MASK 0x7U 41 #define STM32_CLOCK_VAL_SHIFT 16U 42 43 /** 44 * @brief STM32 clock configuration bit field. 45 * 46 * - reg (1/2/3) [ 0 : 7 ] 47 * - shift (0..31) [ 8 : 12 ] 48 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 49 * - val (0..7) [ 16 : 18 ] 50 * 51 * @param reg RCC_CFGRx register offset 52 * @param shift Position within RCC_CFGRx. 53 * @param mask Mask for the RCC_CFGRx field. 54 * @param val Clock value (0, 1, ... 7). 55 */ 56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 57 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 58 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 59 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 60 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 61 62 /** @brief RCC_CFGRx register offset */ 63 #define CFGR_REG 0x04 64 #define CFGR3_REG 0x30 65 66 /** @brief RCC_BDCR register offset */ 67 #define BDCR_REG 0x20 68 69 /** @brief Device domain clocks selection helpers) */ 70 /** CFGR devices */ 71 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) 72 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) 73 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) 74 /** CFGR3 devices */ 75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) 76 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) 77 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG) 78 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) 79 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG) 80 #define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG) 81 #define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG) 82 #define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG) 83 #define TIM17_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG) 84 #define TIM20_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG) 85 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG) 86 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG) 87 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG) 88 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG) 89 #define TIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG) 90 #define TIM3_4_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG) 91 /** BDCR devices */ 92 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 93 94 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */ 95
