1 /*
2  * Copyright (c) 2022 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
8 
9 /** Bus gatting clocks */
10 #define STM32_CLOCK_BUS_AHB1    0x014
11 #define STM32_CLOCK_BUS_APB2    0x018
12 #define STM32_CLOCK_BUS_APB1    0x01c
13 
14 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
15 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB1
16 
17 /** Domain clocks */
18 
19 /** Fixed clocks  */
20 #define STM32_SRC_HSI		0x001
21 #define STM32_SRC_LSE		0x002
22 #define STM32_SRC_LSI		0x003
23 #define STM32_SRC_HSI14		0x004
24 #define STM32_SRC_HSI48		0x005
25 /** System clock */
26 #define STM32_SRC_SYSCLK	0x006
27 /** Bus clock */
28 #define STM32_SRC_PCLK		0x007
29 /** PLL clock */
30 #define STM32_SRC_PLLCLK	0x008
31 
32 #define STM32_CLOCK_REG_MASK    0xFFU
33 #define STM32_CLOCK_REG_SHIFT   0U
34 #define STM32_CLOCK_SHIFT_MASK  0x1FU
35 #define STM32_CLOCK_SHIFT_SHIFT 8U
36 #define STM32_CLOCK_MASK_MASK   0x7U
37 #define STM32_CLOCK_MASK_SHIFT  13U
38 #define STM32_CLOCK_VAL_MASK    0x7U
39 #define STM32_CLOCK_VAL_SHIFT   16U
40 
41 /**
42  * @brief STM32 clock configuration bit field.
43  *
44  * - reg   (1/2/3)         [ 0 : 7 ]
45  * - shift (0..31)         [ 8 : 12 ]
46  * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
47  * - val   (0..7)          [ 16 : 18 ]
48  *
49  * @param reg RCC_CFGRx register offset
50  * @param shift Position within RCC_CFGRx.
51  * @param mask Mask for the RCC_CFGRx field.
52  * @param val Clock value (0, 1, ... 7).
53  */
54 #define STM32_CLOCK(val, mask, shift, reg)					\
55 	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
56 	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
57 	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
58 	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
59 
60 /** @brief RCC_CFGRx register offset */
61 #define CFGR3_REG		0x30
62 
63 /** @brief RCC_BDCR register offset */
64 #define BDCR_REG		0x20
65 
66 /** @brief Device domain clocks selection helpers */
67 /** CFGR3 devices */
68 #define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CFGR3_REG)
69 #define I2C1_SEL(val)		STM32_CLOCK(val, 1, 4, CFGR3_REG)
70 #define CEC_SEL(val)		STM32_CLOCK(val, 1, 6, CFGR3_REG)
71 #define USB_SEL(val)		STM32_CLOCK(val, 1, 7, CFGR3_REG)
72 #define USART2_SEL(val)		STM32_CLOCK(val, 3, 16, CFGR3_REG)
73 #define USART3_SEL(val)		STM32_CLOCK(val, 3, 18, CFGR3_REG)
74 /** BDCR devices */
75 #define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)
76 /** Dummy: Add a specificier when no selection is possible */
77 #define NO_SEL			0xFF
78 
79 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */
80