1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ 9 10 /* PLL 32KHz clock source VTR rail ON. */ 11 #define MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC 0U 12 #define MCHP_XEC_PLL_CLK32K_SRC_XTAL 1U 13 #define MCHP_XEC_PLL_CLK32K_SRC_PIN 2U 14 15 /* Peripheral 32KHz clock source for VTR rail ON and off(VBAT operation) */ 16 #define MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO 0U 17 #define MCHP_XEC_PERIPH_CLK32K_SRC_XTAL_XTAL 1U 18 #define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_SO 2U 19 #define MCHP_XEC_PERIPH_CLK32K_SRC_PIN_XTAL 3U 20 21 /* clocks supported by the driver */ 22 #define MCHP_XEC_PCR_CLK_CORE 0 23 #define MCHP_XEC_PCR_CLK_CPU 1 24 #define MCHP_XEC_PCR_CLK_BUS 2 25 #define MCHP_XEC_PCR_CLK_PERIPH 3 26 #define MCHP_XEC_PCR_CLK_PERIPH_FAST 4 27 #define MCHP_XEC_PCR_CLK_PERIPH_SLOW 5 28 29 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_ */ 30
