1 /* 2 * Copyright (c) 2022 Teslabs Engineering S.L. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ 9 10 #include "gd32-clocks-common.h" 11 12 /** 13 * @name Register offsets 14 * @{ 15 */ 16 17 #define GD32_AHBEN_OFFSET 0x14U 18 #define GD32_APB1EN_OFFSET 0x1CU 19 #define GD32_APB2EN_OFFSET 0x18U 20 #define GD32_ADDAPB1EN_OFFSET 0xE4U 21 22 /** @} */ 23 24 /** 25 * @name Clock enable/disable definitions for peripherals 26 * @{ 27 */ 28 29 /* AHB peripherals */ 30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U) 31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U) 32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U) 33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U) 34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U) 35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U) 36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U) 37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U) 38 39 /* APB1 peripherals */ 40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U) 41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U) 42 #define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U) 43 #define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U) 44 #define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U) 45 #define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U) 46 #define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U) 47 #define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U) 48 #define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U) 49 #define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U) 50 #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U) 51 #define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U) 52 #define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U) 53 #define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U) 54 #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U) 55 #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U) 56 #define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U) 57 #define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U) 58 #define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U) 59 #define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U) 60 #define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U) 61 62 /* APB2 peripherals */ 63 #define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U) 64 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U) 65 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U) 66 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U) 67 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U) 68 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U) 69 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(APB2EN, 7U) 70 #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(APB2EN, 8U) 71 #define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U) 72 #define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U) 73 #define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U) 74 #define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U) 75 #define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U) 76 #define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U) 77 #define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 15U) 78 #define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U) 79 #define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U) 80 #define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U) 81 82 /* APB1 additional peripherals */ 83 #define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U) 84 85 /** @} */ 86 87 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ */ 88