1 /* 2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ 9 10 #include <stdint.h> 11 #include <stdbool.h> 12 #include <soc.h> 13 /* 14 * Interrupt allocation flags - These flags can be used to specify 15 * which interrupt qualities the code calling esp_intr_alloc* needs. 16 */ 17 18 /* Keep the LEVELx values as they are here; they match up with (1<<level) */ 19 #define ESP_INTR_FLAG_LEVEL1 (1<<1) /* Accept a Level 1 int vector, lowest priority */ 20 #define ESP_INTR_FLAG_LEVEL2 (1<<2) /* Accept a Level 2 int vector */ 21 #define ESP_INTR_FLAG_LEVEL3 (1<<3) /* Accept a Level 3 int vector */ 22 #define ESP_INTR_FLAG_LEVEL4 (1<<4) /* Accept a Level 4 int vector */ 23 #define ESP_INTR_FLAG_LEVEL5 (1<<5) /* Accept a Level 5 int vector */ 24 #define ESP_INTR_FLAG_LEVEL6 (1<<6) /* Accept a Level 6 int vector */ 25 #define ESP_INTR_FLAG_NMI (1<<7) /* Accept a Level 7 int vector, highest priority */ 26 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 27 #define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */ 28 #define ESP_INTR_FLAG_IRAM (1<<10) /* ISR can be called if cache is disabled */ 29 #define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */ 30 31 /* Low and medium prio interrupts. These can be handled in C. */ 32 #define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) 33 34 /* High level interrupts. Need to be handled in assembly. */ 35 #define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ 36 ESP_INTR_FLAG_NMI) 37 38 /* Mask for all level flags */ 39 #define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \ 40 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ 41 ESP_INTR_FLAG_NMI) 42 43 #define IRQ_NA 0xFF /* IRQ not available */ 44 #define IRQ_FREE 0xFE /* IRQ available for use */ 45 46 /* 47 * Get the interrupt flags from the supplied priority. 48 */ 49 #define ESP_PRIO_TO_FLAGS(priority) \ 50 ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0) 51 52 /* 53 * Check interrupt flags from input and filter unallowed values. 54 */ 55 #define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED) 56 57 58 /* Function prototype for interrupt handler function */ 59 typedef void (*isr_handler_t)(const void *arg); 60 61 /** 62 * @brief Initializes interrupt table to its defaults 63 */ 64 void esp_intr_initialize(void); 65 66 /** 67 * @brief Allocate an interrupt with the given parameters. 68 * 69 * This finds an interrupt that matches the restrictions as given in the flags 70 * parameter, maps the given interrupt source to it and hooks up the given 71 * interrupt handler (with optional argument) as well. If needed, it can return 72 * a handle for the interrupt as well. 73 * 74 * @param source The interrupt source. 75 * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the 76 * choice of interrupts that this routine can choose from. If this value 77 * is 0, it will default to allocating a non-shared interrupt of level 78 * 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared 79 * interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 80 * from this function with the interrupt disabled. 81 * @param handler The interrupt handler. 82 * @param arg Optional argument for passed to the interrupt handler 83 * @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can 84 * later be used to request details or free the interrupt. Can be NULL if no handle 85 * is required. 86 * 87 * @return -EINVAL if the combination of arguments is invalid. 88 * -ENODEV No free interrupt found with the specified flags 89 * 0 otherwise 90 */ 91 int esp_intr_alloc(int source, 92 int flags, 93 isr_handler_t handler, 94 void *arg, 95 void **ret_handle); 96 97 /** 98 * @brief Disable the interrupt associated with the source 99 * 100 * @param source The interrupt source 101 * 102 * @return -EINVAL if the combination of arguments is invalid. 103 * 0 otherwise 104 */ 105 int esp_intr_disable(int source); 106 107 /** 108 * @brief Enable the interrupt associated with the source 109 * 110 * @param source The interrupt source 111 * @return -EINVAL if the combination of arguments is invalid. 112 * 0 otherwise 113 */ 114 int esp_intr_enable(int source); 115 116 /** 117 * @brief Gets the current enabled interrupts 118 * 119 * @param status_mask_number the status mask can be 0 or 1 120 * @return bitmask of enabled interrupt sources 121 */ 122 uint32_t esp_intr_get_enabled_intmask(int status_mask_number); 123 124 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ */ 125
