1 /* 2 * Copyright (c) 2021 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ 9 10 /* @brief linked_channel value to inform zephyr dma driver that 11 * DMA channel will be handled by HAL 12 */ 13 #define STM32_DMA_HAL_OVERRIDE 0x7F 14 15 /* @brief gives the first DMA channel : 0 or 1 in the register map 16 * when counting channels from 1 to N or from 0 to N-1 17 */ 18 #if defined(CONFIG_DMA_STM32U5) 19 /* from DTS the dma stream id is in range 0..N-1 */ 20 #define STM32_DMA_STREAM_OFFSET 0 21 #elif !defined(CONFIG_DMA_STM32_V1) 22 /* from DTS the dma stream id is in range 1..N */ 23 /* so decrease to set range from 0 from now on */ 24 #define STM32_DMA_STREAM_OFFSET 1 25 #elif defined(CONFIG_DMA_STM32_V1) && defined(CONFIG_DMAMUX_STM32) 26 /* typically on the stm32H7 series, DMA V1 with mux */ 27 #define STM32_DMA_STREAM_OFFSET 1 28 #else 29 /* from DTS the dma stream id is in range 0..N-1 */ 30 #define STM32_DMA_STREAM_OFFSET 0 31 #endif /* ! CONFIG_DMA_STM32_V1 */ 32 33 /* macro for dma slot (only for dma-v1 or dma-v2 types) */ 34 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) 35 #define STM32_DMA_SLOT(id, dir, slot) 0 36 #define STM32_DMA_SLOT_BY_IDX(id, idx, slot) 0 37 #else 38 #define STM32_DMA_SLOT(id, dir, slot) DT_INST_DMAS_CELL_BY_NAME(id, dir, slot) 39 #define STM32_DMA_SLOT_BY_IDX(id, idx, slot) DT_INST_DMAS_CELL_BY_IDX(id, idx, slot) 40 #endif 41 42 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2) || \ 43 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) || \ 44 DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dmamux) 45 #define STM32_DMA_FEATURES(id, dir) 0 46 #else 47 #define STM32_DMA_FEATURES(id, dir) \ 48 DT_INST_DMAS_CELL_BY_NAME(id, dir, features) 49 #endif 50 51 #define STM32_DMA_CTLR(id, dir) \ 52 DT_INST_DMAS_CTLR_BY_NAME(id, dir) 53 #define STM32_DMA_CHANNEL_CONFIG(id, dir) \ 54 DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config) 55 #define STM32_DMA_CHANNEL_CONFIG_BY_IDX(id, idx) \ 56 DT_INST_DMAS_CELL_BY_IDX(id, idx, channel_config) 57 58 /* macros for channel-config */ 59 /* direction defined on bits 6-7 */ 60 /* 0 -> MEM_TO_MEM, 1 -> MEM_TO_PERIPH, 2 -> PERIPH_TO_MEM */ 61 #define STM32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3) 62 /* periph increment defined on bit 9 as true/false */ 63 #define STM32_DMA_CONFIG_PERIPHERAL_ADDR_INC(config) ((config >> 9) & 0x1) 64 /* mem increment defined on bit 10 as true/false */ 65 #define STM32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1) 66 /* periph data size defined on bits 11-12 */ 67 /* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */ 68 #define STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE(config) \ 69 (1 << ((config >> 11) & 0x3)) 70 /* memory data size defined on bits 13, 14 */ 71 /* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */ 72 #define STM32_DMA_CONFIG_MEMORY_DATA_SIZE(config) \ 73 (1 << ((config >> 13) & 0x3)) 74 /* priority increment offset defined on bit 15 */ 75 #define STM32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1) 76 /* priority defined on bits 16-17 as 0, 1, 2, 3 */ 77 #define STM32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3) 78 79 /* macro for features (only for dma-v1) */ 80 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1) 81 #define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) (features & 0x3) 82 #else 83 #define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) 0 84 #endif 85 86 #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ */ 87
