1 /* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_ 7 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_ 8 9 #include <zephyr/drivers/clock_control.h> 10 #include <zephyr/dt-bindings/clock/ra_clock.h> 11 12 #define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ 13 COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) 14 15 #define RA_CGC_CLK_SRC(node_id) \ 16 COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ 17 (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ 18 (BSP_CLOCKS_CLOCK_DISABLED)) 19 20 #define RA_CGC_CLK_DIV(clk, prop, default_value) \ 21 UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ 22 (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value)) 23 24 #define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 25 #define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n) 26 #define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n) 27 #define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n) 28 #define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 29 #define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 30 #define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n) 31 #define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 32 #define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n) 33 #define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n) 34 #define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 35 #define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 36 #define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 37 #define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 38 #define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) 39 #define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 40 #define RA_CGC_DIV_PLLP(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 41 #define RA_CGC_DIV_PLLQ(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 42 #define RA_CGC_DIV_PLLR(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 43 #define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 44 #define RA_CGC_DIV_PLL2P(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 45 #define RA_CGC_DIV_PLL2Q(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 46 #define RA_CGC_DIV_PLL2R(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) 47 #define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) 48 #define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) 49 #define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) 50 #define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) 51 52 #define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL 53 #define BSP_CLOCKS_SOURCE_PLLP BSP_CLOCKS_SOURCE_CLOCK_PLL 54 #define BSP_CLOCKS_SOURCE_PLLQ BSP_CLOCKS_SOURCE_CLOCK_PLL1Q 55 #define BSP_CLOCKS_SOURCE_PLLR BSP_CLOCKS_SOURCE_CLOCK_PLL1R 56 57 #define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL2 58 #define BSP_CLOCKS_SOURCE_PLL2P BSP_CLOCKS_SOURCE_CLOCK_PLL2 59 #define BSP_CLOCKS_SOURCE_PLL2Q BSP_CLOCKS_SOURCE_CLOCK_PLL2Q 60 #define BSP_CLOCKS_SOURCE_PLL2R BSP_CLOCKS_SOURCE_CLOCK_PLL2R 61 62 #define BSP_CLOCKS_CLKOUT_DIV_1 (0) 63 #define BSP_CLOCKS_CLKOUT_DIV_2 (1) 64 #define BSP_CLOCKS_CLKOUT_DIV_4 (2) 65 #define BSP_CLOCKS_CLKOUT_DIV_8 (3) 66 #define BSP_CLOCKS_CLKOUT_DIV_16 (4) 67 #define BSP_CLOCKS_CLKOUT_DIV_32 (5) 68 #define BSP_CLOCKS_CLKOUT_DIV_64 (6) 69 #define BSP_CLOCKS_CLKOUT_DIV_128 (7) 70 71 struct clock_control_ra_pclk_cfg { 72 uint32_t clk_src; 73 uint32_t clk_div; 74 }; 75 76 struct clock_control_ra_subsys_cfg { 77 uint32_t mstp; 78 uint32_t stop_bit; 79 }; 80 81 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_ */ 82
