1 /* 2 * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief API for NXP SJA1000 (and compatible) CAN controller frontend drivers. 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_ 13 #define ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_ 14 15 #include <zephyr/drivers/can.h> 16 17 /** 18 * @name SJA1000 Output Control Register (OCR) bits 19 * 20 * @{ 21 */ 22 #define CAN_SJA1000_OCR_OCMODE_MASK GENMASK(1, 0) 23 #define CAN_SJA1000_OCR_OCPOL0 BIT(2) 24 #define CAN_SJA1000_OCR_OCTN0 BIT(3) 25 #define CAN_SJA1000_OCR_OCTP0 BIT(4) 26 #define CAN_SJA1000_OCR_OCPOL1 BIT(5) 27 #define CAN_SJA1000_OCR_OCTN1 BIT(6) 28 #define CAN_SJA1000_OCR_OCTP1 BIT(7) 29 30 #define CAN_SJA1000_OCR_OCMODE_BIPHASE FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 0U) 31 #define CAN_SJA1000_OCR_OCMODE_TEST FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 1U) 32 #define CAN_SJA1000_OCR_OCMODE_NORMAL FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 2U) 33 #define CAN_SJA1000_OCR_OCMODE_CLOCK FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 3U) 34 35 /** @} */ 36 37 /** 38 * @name SJA1000 Clock Divider Register (CDR) bits 39 * 40 * @{ 41 */ 42 #define CAN_SJA1000_CDR_CD_MASK GENMASK(2, 0) 43 #define CAN_SJA1000_CDR_CLOCK_OFF BIT(3) 44 #define CAN_SJA1000_CDR_RXINTEN BIT(5) 45 #define CAN_SJA1000_CDR_CBP BIT(6) 46 #define CAN_SJA1000_CDR_CAN_MODE BIT(7) 47 48 #define CAN_SJA1000_CDR_CD_DIV1 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 7U) 49 #define CAN_SJA1000_CDR_CD_DIV2 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 0U) 50 #define CAN_SJA1000_CDR_CD_DIV4 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 1U) 51 #define CAN_SJA1000_CDR_CD_DIV6 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 2U) 52 #define CAN_SJA1000_CDR_CD_DIV8 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 3U) 53 #define CAN_SJA1000_CDR_CD_DIV10 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 4U) 54 #define CAN_SJA1000_CDR_CD_DIV12 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 5U) 55 #define CAN_SJA1000_CDR_CD_DIV14 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 6U) 56 57 /** @} */ 58 59 /** 60 * @brief SJA1000 specific static initializer for a minimum @p can_timing struct 61 */ 62 #define CAN_SJA1000_TIMING_MIN_INITIALIZER \ 63 { \ 64 .sjw = 1, \ 65 .prop_seg = 0, \ 66 .phase_seg1 = 1, \ 67 .phase_seg2 = 1, \ 68 .prescaler = 1 \ 69 } 70 71 /** 72 * @brief SJA1000 specific static initializer for a maximum @p can_timing struct 73 */ 74 #define CAN_SJA1000_TIMING_MAX_INITIALIZER \ 75 { \ 76 .sjw = 4, \ 77 .prop_seg = 0, \ 78 .phase_seg1 = 16, \ 79 .phase_seg2 = 8, \ 80 .prescaler = 64 \ 81 } 82 83 /** 84 * @brief SJA1000 driver front-end callback for writing a register value 85 * 86 * @param dev Pointer to the device structure for the driver instance. 87 * @param reg Register offset 88 * @param val Register value 89 */ 90 typedef void (*can_sja1000_write_reg_t)(const struct device *dev, uint8_t reg, uint8_t val); 91 92 /** 93 * @brief SJA1000 driver front-end callback for reading a register value 94 * 95 * @param dev Pointer to the device structure for the driver instance. 96 * @param reg Register offset 97 * @retval Register value 98 */ 99 typedef uint8_t (*can_sja1000_read_reg_t)(const struct device *dev, uint8_t reg); 100 101 /** 102 * @brief SJA1000 driver internal configuration structure. 103 */ 104 struct can_sja1000_config { 105 can_sja1000_read_reg_t read_reg; 106 can_sja1000_write_reg_t write_reg; 107 uint32_t bitrate; 108 uint32_t sample_point; 109 uint32_t sjw; 110 uint32_t phase_seg1; 111 uint32_t phase_seg2; 112 const struct device *phy; 113 uint32_t max_bitrate; 114 uint8_t ocr; 115 uint8_t cdr; 116 const void *custom; 117 }; 118 119 /** 120 * @brief Static initializer for @p can_sja1000_config struct 121 * 122 * @param node_id Devicetree node identifier 123 * @param _custom Pointer to custom driver frontend configuration structure 124 * @param _read_reg Driver frontend SJA100 register read function 125 * @param _write_reg Driver frontend SJA100 register write function 126 * @param _ocr Initial SJA1000 Output Control Register (OCR) value 127 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value 128 */ 129 #define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr) \ 130 { \ 131 .read_reg = _read_reg, .write_reg = _write_reg, \ 132 .bitrate = DT_PROP(node_id, bus_speed), .sjw = DT_PROP(node_id, sjw), \ 133 .phase_seg1 = DT_PROP_OR(node_id, phase_seg1, 0), \ 134 .phase_seg2 = DT_PROP_OR(node_id, phase_seg2, 0), \ 135 .sample_point = DT_PROP_OR(node_id, sample_point, 0), \ 136 .max_bitrate = DT_CAN_TRANSCEIVER_MAX_BITRATE(node_id, 1000000), \ 137 .phy = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, phys)), \ 138 .ocr = _ocr, .cdr = _cdr, .custom = _custom, \ 139 } 140 141 /** 142 * @brief Static initializer for @p can_sja1000_config struct from a DT_DRV_COMPAT instance 143 * 144 * @param inst DT_DRV_COMPAT instance number 145 * @param _custom Pointer to custom driver frontend configuration structure 146 * @param _read_reg Driver frontend SJA100 register read function 147 * @param _write_reg Driver frontend SJA100 register write function 148 * @param _ocr Initial SJA1000 Output Control Register (OCR) value 149 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value 150 * @see CAN_SJA1000_DT_CONFIG_GET() 151 */ 152 #define CAN_SJA1000_DT_CONFIG_INST_GET(inst, _custom, _read_reg, _write_reg, _ocr, _cdr) \ 153 CAN_SJA1000_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _read_reg, _write_reg, _ocr, _cdr) 154 155 /** 156 * @brief SJA1000 driver internal RX filter structure. 157 */ 158 struct can_sja1000_rx_filter { 159 struct can_filter filter; 160 can_rx_callback_t callback; 161 void *user_data; 162 }; 163 164 /** 165 * @brief SJA1000 driver internal data structure. 166 */ 167 struct can_sja1000_data { 168 ATOMIC_DEFINE(rx_allocs, CONFIG_CAN_MAX_FILTER); 169 struct can_sja1000_rx_filter filters[CONFIG_CAN_MAX_FILTER]; 170 struct k_mutex mod_lock; 171 bool started; 172 can_mode_t mode; 173 enum can_state state; 174 can_state_change_callback_t state_change_cb; 175 void *state_change_cb_data; 176 struct k_sem tx_idle; 177 can_tx_callback_t tx_callback; 178 void *tx_user_data; 179 void *custom; 180 }; 181 182 /** 183 * @brief Initializer for a @a can_sja1000_data struct 184 * @param _custom Pointer to custom driver frontend data structure 185 */ 186 #define CAN_SJA1000_DATA_INITIALIZER(_custom) \ 187 { \ 188 .custom = _custom, \ 189 } 190 191 /** 192 * @brief SJA1000 callback API upon setting CAN bus timing 193 * See @a can_set_timing() for argument description 194 */ 195 int can_sja1000_set_timing(const struct device *dev, const struct can_timing *timing); 196 197 /** 198 * @brief SJA1000 callback API upon getting CAN controller capabilities 199 * See @a can_get_capabilities() for argument description 200 */ 201 int can_sja1000_get_capabilities(const struct device *dev, can_mode_t *cap); 202 203 /** 204 * @brief SJA1000 callback API upon starting CAN controller 205 * See @a can_start() for argument description 206 */ 207 int can_sja1000_start(const struct device *dev); 208 209 /** 210 * @brief SJA1000 callback API upon stopping CAN controller 211 * See @a can_stop() for argument description 212 */ 213 int can_sja1000_stop(const struct device *dev); 214 215 /** 216 * @brief SJA1000 callback API upon setting CAN controller mode 217 * See @a can_set_mode() for argument description 218 */ 219 int can_sja1000_set_mode(const struct device *dev, can_mode_t mode); 220 221 /** 222 * @brief SJA1000 callback API upon sending a CAN frame 223 * See @a can_send() for argument description 224 */ 225 int can_sja1000_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout, 226 can_tx_callback_t callback, void *user_data); 227 228 /** 229 * @brief SJA1000 callback API upon adding an RX filter 230 * See @a can_add_rx_callback() for argument description 231 */ 232 int can_sja1000_add_rx_filter(const struct device *dev, can_rx_callback_t callback, void *user_data, 233 const struct can_filter *filter); 234 235 /** 236 * @brief SJA1000 callback API upon removing an RX filter 237 * See @a can_remove_rx_filter() for argument description 238 */ 239 void can_sja1000_remove_rx_filter(const struct device *dev, int filter_id); 240 241 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY 242 /** 243 * @brief SJA1000 callback API upon recovering the CAN bus 244 * See @a can_recover() for argument description 245 */ 246 int can_sja1000_recover(const struct device *dev, k_timeout_t timeout); 247 #endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ 248 249 /** 250 * @brief SJA1000 callback API upon getting the CAN controller state 251 * See @a can_get_state() for argument description 252 */ 253 int can_sja1000_get_state(const struct device *dev, enum can_state *state, 254 struct can_bus_err_cnt *err_cnt); 255 256 /** 257 * @brief SJA1000 callback API upon setting a state change callback 258 * See @a can_set_state_change_callback() for argument description 259 */ 260 void can_sja1000_set_state_change_callback(const struct device *dev, 261 can_state_change_callback_t callback, void *user_data); 262 263 /** 264 * @brief SJA1000 callback API upon getting the maximum number of concurrent CAN RX filters 265 * See @a can_get_max_filters() for argument description 266 */ 267 int can_sja1000_get_max_filters(const struct device *dev, bool ide); 268 269 /** 270 * @brief SJA1000 callback API upon getting the maximum supported bitrate 271 * See @a can_get_max_bitrate() for argument description 272 */ 273 int can_sja1000_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate); 274 275 /** 276 * @brief SJA1000 IRQ handler callback. 277 * 278 * @param dev Pointer to the device structure for the driver instance. 279 */ 280 void can_sja1000_isr(const struct device *dev); 281 282 /** 283 * @brief SJA1000 driver initialization callback. 284 * 285 * @param dev Pointer to the device structure for the driver instance. 286 */ 287 int can_sja1000_init(const struct device *dev); 288 289 #endif /* ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_SJA1000_H_ */ 290
